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authorPaul Walmsley <paul@pwsan.com>2008-03-18 04:04:51 -0400
committerTony Lindgren <tony@atomide.com>2008-04-14 13:29:37 -0400
commit445959821f82846913fe09fee0573e0238415e8c (patch)
tree38d0ec8fd827017e21961a42a58a9bcaaede7c6e /arch/arm/mach-omap2/gpmc.c
parentc595713da76bc7cedddf5135072ea6037cc0befb (diff)
ARM: OMAP2: Change 24xx to use new register access
This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/gpmc.c')
-rw-r--r--arch/arm/mach-omap2/gpmc.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5a4cc2076a7d..02cede295e89 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -69,7 +69,7 @@ static void __iomem *gpmc_base =
69static void __iomem *gpmc_cs_base = 69static void __iomem *gpmc_cs_base =
70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0; 70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
71 71
72static struct clk *gpmc_l3_clk; 72static struct clk *gpmc_fck;
73 73
74static void gpmc_write_reg(int idx, u32 val) 74static void gpmc_write_reg(int idx, u32 val)
75{ 75{
@@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx)
94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); 94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
95} 95}
96 96
97/* TODO: Add support for gpmc_fck to clock framework and use it */
98unsigned long gpmc_get_fclk_period(void) 97unsigned long gpmc_get_fclk_period(void)
99{ 98{
100 /* In picoseconds */ 99 /* In picoseconds */
101 return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); 100 return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
102} 101}
103 102
104unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 103unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -398,8 +397,11 @@ void __init gpmc_init(void)
398{ 397{
399 u32 l; 398 u32 l;
400 399
401 gpmc_l3_clk = clk_get(NULL, "core_l3_ck"); 400 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
402 BUG_ON(IS_ERR(gpmc_l3_clk)); 401 if (IS_ERR(gpmc_fck))
402 WARN_ON(1);
403 else
404 clk_enable(gpmc_fck);
403 405
404 l = gpmc_read_reg(GPMC_REVISION); 406 l = gpmc_read_reg(GPMC_REVISION);
405 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 407 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);