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authorAfzal Mohammed <afzal@ti.com>2012-08-17 01:59:14 -0400
committerAfzal Mohammed <afzal@ti.com>2012-11-09 07:37:22 -0500
commitac2d9ae1947288677ec78cd91a29490234ab9854 (patch)
treedb004f003f8fc1fd14de214b461b530be169d6b0 /arch/arm/mach-omap2/gpmc-smc91x.c
parent4f4426f900bb8a9efcdbcc8bcc94708763e1ed15 (diff)
ARM: OMAP2+: smc91x: generic timing calculation
Generic gpmc timing calculation helper is available now, use it instead of custom timing calculation. Signed-off-by: Afzal Mohammed <afzal@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/gpmc-smc91x.c')
-rw-r--r--arch/arm/mach-omap2/gpmc-smc91x.c43
1 files changed, 17 insertions, 26 deletions
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 6eed907d594c..11d0b756f098 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -58,6 +58,7 @@ static struct platform_device gpmc_smc91x_device = {
58static int smc91c96_gpmc_retime(void) 58static int smc91c96_gpmc_retime(void)
59{ 59{
60 struct gpmc_timings t; 60 struct gpmc_timings t;
61 struct gpmc_device_timings dev_t;
61 const int t3 = 10; /* Figure 12.2 read and 12.4 write */ 62 const int t3 = 10; /* Figure 12.2 read and 12.4 write */
62 const int t4_r = 20; /* Figure 12.2 read */ 63 const int t4_r = 20; /* Figure 12.2 read */
63 const int t4_w = 5; /* Figure 12.4 write */ 64 const int t4_w = 5; /* Figure 12.4 write */
@@ -68,32 +69,6 @@ static int smc91c96_gpmc_retime(void)
68 const int t20 = 185; /* Figure 12.2 read and 12.4 write */ 69 const int t20 = 185; /* Figure 12.2 read and 12.4 write */
69 u32 l; 70 u32 l;
70 71
71 memset(&t, 0, sizeof(t));
72
73 /* Read timings */
74 t.cs_on = 0;
75 t.adv_on = t.cs_on;
76 t.oe_on = t.adv_on + t3;
77 t.access = t.oe_on + t5;
78 t.oe_off = t.access;
79 t.adv_rd_off = t.oe_off + max(t4_r, t6);
80 t.cs_rd_off = t.oe_off;
81 t.rd_cycle = t20 - t.oe_on;
82
83 /* Write timings */
84 t.we_on = t.adv_on + t3;
85
86 if (cpu_is_omap34xx() && (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)) {
87 t.wr_data_mux_bus = t.we_on;
88 t.we_off = t.wr_data_mux_bus + t7;
89 } else
90 t.we_off = t.we_on + t7;
91 if (cpu_is_omap34xx())
92 t.wr_access = t.we_off;
93 t.adv_wr_off = t.we_off + max(t4_w, t8);
94 t.cs_wr_off = t.we_off + t4_w;
95 t.wr_cycle = t20 - t.we_on;
96
97 l = GPMC_CONFIG1_DEVICESIZE_16; 72 l = GPMC_CONFIG1_DEVICESIZE_16;
98 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA) 73 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
99 l |= GPMC_CONFIG1_MUXADDDATA; 74 l |= GPMC_CONFIG1_MUXADDDATA;
@@ -115,6 +90,22 @@ static int smc91c96_gpmc_retime(void)
115 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA) 90 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
116 return 0; 91 return 0;
117 92
93 memset(&dev_t, 0, sizeof(dev_t));
94
95 dev_t.t_oeasu = t3 * 1000;
96 dev_t.t_oe = t5 * 1000;
97 dev_t.t_cez_r = t4_r * 1000;
98 dev_t.t_oez = t6 * 1000;
99 dev_t.t_rd_cycle = (t20 - t3) * 1000;
100
101 dev_t.t_weasu = t3 * 1000;
102 dev_t.t_wpl = t7 * 1000;
103 dev_t.t_wph = t8 * 1000;
104 dev_t.t_cez_w = t4_w * 1000;
105 dev_t.t_wr_cycle = (t20 - t3) * 1000;
106
107 gpmc_calc_timings(&t, &dev_t);
108
118 return gpmc_cs_set_timings(gpmc_cfg->cs, &t); 109 return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
119} 110}
120 111