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authorAdrian Hunter <adrian.hunter@nokia.com>2011-02-07 03:46:59 -0500
committerTony Lindgren <tony@atomide.com>2011-02-17 18:44:45 -0500
commit3ad2d861362031dac8b2bba78a8f4c575300948f (patch)
tree24dbf3d99034234dac78b3c001eac5c8470d514b /arch/arm/mach-omap2/gpmc-onenand.c
parent1435ca0fc1a269f9496343e24223a0fc430aff7a (diff)
OMAP: OneNAND: determine frequency in one place
OneNAND frequency is determined when calculating GPMC timings. Return that value instead of determining it again in the OMAP OneNAND driver. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/gpmc-onenand.c')
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 3a4307b8f7cf..46786a606e90 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -123,7 +123,7 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
123 123
124static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, 124static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
125 void __iomem *onenand_base, 125 void __iomem *onenand_base,
126 int freq) 126 int *freq_ptr)
127{ 127{
128 struct gpmc_timings t; 128 struct gpmc_timings t;
129 const int t_cer = 15; 129 const int t_cer = 15;
@@ -136,7 +136,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
136 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; 136 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
137 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; 137 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
138 int err, ticks_cez; 138 int err, ticks_cez;
139 int cs = cfg->cs; 139 int cs = cfg->cs, freq = *freq_ptr;
140 u32 reg; 140 u32 reg;
141 141
142 if (cfg->flags & ONENAND_SYNC_READ) { 142 if (cfg->flags & ONENAND_SYNC_READ) {
@@ -330,16 +330,18 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
330 330
331 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); 331 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
332 332
333 *freq_ptr = freq;
334
333 return 0; 335 return 0;
334} 336}
335 337
336static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) 338static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
337{ 339{
338 struct device *dev = &gpmc_onenand_device.dev; 340 struct device *dev = &gpmc_onenand_device.dev;
339 341
340 /* Set sync timings in GPMC */ 342 /* Set sync timings in GPMC */
341 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, 343 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
342 freq) < 0) { 344 freq_ptr) < 0) {
343 dev_err(dev, "Unable to set synchronous mode\n"); 345 dev_err(dev, "Unable to set synchronous mode\n");
344 return -EINVAL; 346 return -EINVAL;
345 } 347 }