diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-12-09 17:38:28 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-12-09 17:38:28 -0500 |
commit | 6cd94d5e57ab97ddd672b707ab4bb639672c1727 (patch) | |
tree | b1b301b16433d4deab6bd52e81d04a7b58c239d3 /arch/arm/mach-omap2/dpll44xx.c | |
parent | 6c9e92476bc924ede6d6d2f0bfed2c06ae148d29 (diff) | |
parent | 842f7d2c4d392c0571cf72e3eaca26742bebbd1e (diff) |
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
Diffstat (limited to 'arch/arm/mach-omap2/dpll44xx.c')
-rw-r--r-- | arch/arm/mach-omap2/dpll44xx.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 4613f1e86988..535822fcf4bb 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c | |||
@@ -207,3 +207,44 @@ out: | |||
207 | 207 | ||
208 | return dd->last_rounded_rate; | 208 | return dd->last_rounded_rate; |
209 | } | 209 | } |
210 | |||
211 | /** | ||
212 | * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL | ||
213 | * @hw: pointer to the clock to determine rate for | ||
214 | * @rate: target rate for the DPLL | ||
215 | * @best_parent_rate: pointer for returning best parent rate | ||
216 | * @best_parent_clk: pointer for returning best parent clock | ||
217 | * | ||
218 | * Determines which DPLL mode to use for reaching a desired rate. | ||
219 | * Checks whether the DPLL shall be in bypass or locked mode, and if | ||
220 | * locked, calculates the M,N values for the DPLL via round-rate. | ||
221 | * Returns a positive clock rate with success, negative error value | ||
222 | * in failure. | ||
223 | */ | ||
224 | long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, | ||
225 | unsigned long *best_parent_rate, | ||
226 | struct clk **best_parent_clk) | ||
227 | { | ||
228 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | ||
229 | struct dpll_data *dd; | ||
230 | |||
231 | if (!hw || !rate) | ||
232 | return -EINVAL; | ||
233 | |||
234 | dd = clk->dpll_data; | ||
235 | if (!dd) | ||
236 | return -EINVAL; | ||
237 | |||
238 | if (__clk_get_rate(dd->clk_bypass) == rate && | ||
239 | (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | ||
240 | *best_parent_clk = dd->clk_bypass; | ||
241 | } else { | ||
242 | rate = omap4_dpll_regm4xen_round_rate(hw, rate, | ||
243 | best_parent_rate); | ||
244 | *best_parent_clk = dd->clk_ref; | ||
245 | } | ||
246 | |||
247 | *best_parent_rate = rate; | ||
248 | |||
249 | return rate; | ||
250 | } | ||