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authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-21 15:30:30 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-21 15:30:30 -0500
commit18a8d49973667aa016e68826eeb374788b7c63b0 (patch)
treed7f90fcf05087ce50ee931b596e60e4c3c082a29 /arch/arm/mach-omap2/dpll3xxx.c
parentc189cb8ef62832f33b6cf757350a0270532a1ad8 (diff)
parentec02ace8ca0a50eef430d3676de5c5fa978b0e29 (diff)
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
Diffstat (limited to 'arch/arm/mach-omap2/dpll3xxx.c')
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index c2da2a0fe5ad..44e57ec225d4 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -410,7 +410,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
410 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 410 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
411 int r; 411 int r;
412 struct dpll_data *dd; 412 struct dpll_data *dd;
413 struct clk *parent; 413 struct clk_hw *parent;
414 414
415 dd = clk->dpll_data; 415 dd = clk->dpll_data;
416 if (!dd) 416 if (!dd)
@@ -427,13 +427,13 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
427 } 427 }
428 } 428 }
429 429
430 parent = __clk_get_parent(hw->clk); 430 parent = __clk_get_hw(__clk_get_parent(hw->clk));
431 431
432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { 432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
433 WARN_ON(parent != dd->clk_bypass); 433 WARN_ON(parent != __clk_get_hw(dd->clk_bypass));
434 r = _omap3_noncore_dpll_bypass(clk); 434 r = _omap3_noncore_dpll_bypass(clk);
435 } else { 435 } else {
436 WARN_ON(parent != dd->clk_ref); 436 WARN_ON(parent != __clk_get_hw(dd->clk_ref));
437 r = _omap3_noncore_dpll_lock(clk); 437 r = _omap3_noncore_dpll_lock(clk);
438 } 438 }
439 439
@@ -473,6 +473,8 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
473 * in failure. 473 * in failure.
474 */ 474 */
475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, 475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
476 unsigned long min_rate,
477 unsigned long max_rate,
476 unsigned long *best_parent_rate, 478 unsigned long *best_parent_rate,
477 struct clk_hw **best_parent_clk) 479 struct clk_hw **best_parent_clk)
478{ 480{
@@ -549,7 +551,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
549 if (!dd) 551 if (!dd)
550 return -EINVAL; 552 return -EINVAL;
551 553
552 if (__clk_get_parent(hw->clk) != dd->clk_ref) 554 if (__clk_get_hw(__clk_get_parent(hw->clk)) !=
555 __clk_get_hw(dd->clk_ref))
553 return -EINVAL; 556 return -EINVAL;
554 557
555 if (dd->last_rounded_rate == 0) 558 if (dd->last_rounded_rate == 0)