diff options
author | Rajendra Nayak <rnayak@ti.com> | 2009-12-08 20:47:16 -0500 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-12-11 19:00:46 -0500 |
commit | 16975a79c8e6ee424331f52649f2351d33c7b972 (patch) | |
tree | 4efc6d4329e467b7c12a8838f544d6cfe928735e /arch/arm/mach-omap2/dpll.c | |
parent | a1391d276866845018920329bc2a3a82ab322af8 (diff) |
ARM: OMAP4: PM: Add support for OMAP4 dpll api's
Most of the dpll api's from dpll.c are reused for OMAP4.
This patch does extend a few api's for OMAP4 support.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/dpll.c')
-rw-r--r-- | arch/arm/mach-omap2/dpll.c | 28 |
1 files changed, 17 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll.c index a39fe9d8c278..f6055b493294 100644 --- a/arch/arm/mach-omap2/dpll.c +++ b/arch/arm/mach-omap2/dpll.c | |||
@@ -26,9 +26,9 @@ | |||
26 | #include <linux/limits.h> | 26 | #include <linux/limits.h> |
27 | #include <linux/bitops.h> | 27 | #include <linux/bitops.h> |
28 | 28 | ||
29 | #include <mach/cpu.h> | 29 | #include <plat/cpu.h> |
30 | #include <mach/clock.h> | 30 | #include <plat/clock.h> |
31 | #include <mach/sram.h> | 31 | #include <plat/sram.h> |
32 | #include <asm/div64.h> | 32 | #include <asm/div64.h> |
33 | #include <asm/clkdev.h> | 33 | #include <asm/clkdev.h> |
34 | 34 | ||
@@ -311,10 +311,12 @@ int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |||
311 | _omap3_noncore_dpll_bypass(clk); | 311 | _omap3_noncore_dpll_bypass(clk); |
312 | 312 | ||
313 | /* Set jitter correction */ | 313 | /* Set jitter correction */ |
314 | v = __raw_readl(dd->control_reg); | 314 | if (!cpu_is_omap44xx()) { |
315 | v &= ~dd->freqsel_mask; | 315 | v = __raw_readl(dd->control_reg); |
316 | v |= freqsel << __ffs(dd->freqsel_mask); | 316 | v &= ~dd->freqsel_mask; |
317 | __raw_writel(v, dd->control_reg); | 317 | v |= freqsel << __ffs(dd->freqsel_mask); |
318 | __raw_writel(v, dd->control_reg); | ||
319 | } | ||
318 | 320 | ||
319 | /* Set DPLL multiplier, divider */ | 321 | /* Set DPLL multiplier, divider */ |
320 | v = __raw_readl(dd->mult_div1_reg); | 322 | v = __raw_readl(dd->mult_div1_reg); |
@@ -346,7 +348,7 @@ int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |||
346 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | 348 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) |
347 | { | 349 | { |
348 | struct clk *new_parent = NULL; | 350 | struct clk *new_parent = NULL; |
349 | u16 freqsel; | 351 | u16 freqsel = 0; |
350 | struct dpll_data *dd; | 352 | struct dpll_data *dd; |
351 | int ret; | 353 | int ret; |
352 | 354 | ||
@@ -382,9 +384,13 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |||
382 | if (dd->last_rounded_rate == 0) | 384 | if (dd->last_rounded_rate == 0) |
383 | return -EINVAL; | 385 | return -EINVAL; |
384 | 386 | ||
385 | freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); | 387 | /* No freqsel on OMAP4 */ |
386 | if (!freqsel) | 388 | if (!cpu_is_omap44xx()) { |
387 | WARN_ON(1); | 389 | freqsel = _omap3_dpll_compute_freqsel(clk, |
390 | dd->last_rounded_n); | ||
391 | if (!freqsel) | ||
392 | WARN_ON(1); | ||
393 | } | ||
388 | 394 | ||
389 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | 395 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", |
390 | clk->name, rate); | 396 | clk->name, rate); |