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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2011-02-11 10:12:12 -0500
committerKevin Hilman <khilman@ti.com>2011-03-09 19:15:50 -0500
commit8c5ca4d29bf44eb4eb004683ca745742040c7486 (patch)
treecabadba22a161c854afcfbb0fdb9c7760cf4b589 /arch/arm/mach-omap2/cpuidle34xx.c
parent261bfb286eab32aa6129f48d2b2d24f20825757b (diff)
omap3: cpuidle: Add description field to each C-state.
Add a description field to each idle C-state. This helps to give better data with PowerTop and one don't have to refer to the code to link what Cx means from system point of view while analysing PowerTop data. No functional change. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/cpuidle34xx.c')
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 876eecab9f4d..cba437dd002b 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -58,6 +58,7 @@ struct omap3_processor_cx {
58 u32 core_state; 58 u32 core_state;
59 u32 threshold; 59 u32 threshold;
60 u32 flags; 60 u32 flags;
61 const char *desc;
61}; 62};
62 63
63struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; 64struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
@@ -365,6 +366,7 @@ void omap_init_power_states(void)
365 omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; 366 omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
366 omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; 367 omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
367 omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; 368 omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
369 omap3_power_states[OMAP3_STATE_C1].desc = "MPU ON + CORE ON";
368 370
369 /* C2 . MPU WFI + Core inactive */ 371 /* C2 . MPU WFI + Core inactive */
370 omap3_power_states[OMAP3_STATE_C2].valid = 372 omap3_power_states[OMAP3_STATE_C2].valid =
@@ -380,6 +382,7 @@ void omap_init_power_states(void)
380 omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; 382 omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
381 omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | 383 omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
382 CPUIDLE_FLAG_CHECK_BM; 384 CPUIDLE_FLAG_CHECK_BM;
385 omap3_power_states[OMAP3_STATE_C2].desc = "MPU ON + CORE ON";
383 386
384 /* C3 . MPU CSWR + Core inactive */ 387 /* C3 . MPU CSWR + Core inactive */
385 omap3_power_states[OMAP3_STATE_C3].valid = 388 omap3_power_states[OMAP3_STATE_C3].valid =
@@ -395,6 +398,7 @@ void omap_init_power_states(void)
395 omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; 398 omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
396 omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | 399 omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
397 CPUIDLE_FLAG_CHECK_BM; 400 CPUIDLE_FLAG_CHECK_BM;
401 omap3_power_states[OMAP3_STATE_C3].desc = "MPU RET + CORE ON";
398 402
399 /* C4 . MPU OFF + Core inactive */ 403 /* C4 . MPU OFF + Core inactive */
400 omap3_power_states[OMAP3_STATE_C4].valid = 404 omap3_power_states[OMAP3_STATE_C4].valid =
@@ -410,6 +414,7 @@ void omap_init_power_states(void)
410 omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; 414 omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
411 omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | 415 omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
412 CPUIDLE_FLAG_CHECK_BM; 416 CPUIDLE_FLAG_CHECK_BM;
417 omap3_power_states[OMAP3_STATE_C4].desc = "MPU OFF + CORE ON";
413 418
414 /* C5 . MPU CSWR + Core CSWR*/ 419 /* C5 . MPU CSWR + Core CSWR*/
415 omap3_power_states[OMAP3_STATE_C5].valid = 420 omap3_power_states[OMAP3_STATE_C5].valid =
@@ -425,6 +430,7 @@ void omap_init_power_states(void)
425 omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; 430 omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
426 omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | 431 omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
427 CPUIDLE_FLAG_CHECK_BM; 432 CPUIDLE_FLAG_CHECK_BM;
433 omap3_power_states[OMAP3_STATE_C5].desc = "MPU RET + CORE RET";
428 434
429 /* C6 . MPU OFF + Core CSWR */ 435 /* C6 . MPU OFF + Core CSWR */
430 omap3_power_states[OMAP3_STATE_C6].valid = 436 omap3_power_states[OMAP3_STATE_C6].valid =
@@ -440,6 +446,7 @@ void omap_init_power_states(void)
440 omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; 446 omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
441 omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | 447 omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
442 CPUIDLE_FLAG_CHECK_BM; 448 CPUIDLE_FLAG_CHECK_BM;
449 omap3_power_states[OMAP3_STATE_C6].desc = "MPU OFF + CORE RET";
443 450
444 /* C7 . MPU OFF + Core OFF */ 451 /* C7 . MPU OFF + Core OFF */
445 omap3_power_states[OMAP3_STATE_C7].valid = 452 omap3_power_states[OMAP3_STATE_C7].valid =
@@ -455,6 +462,7 @@ void omap_init_power_states(void)
455 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; 462 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
456 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | 463 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
457 CPUIDLE_FLAG_CHECK_BM; 464 CPUIDLE_FLAG_CHECK_BM;
465 omap3_power_states[OMAP3_STATE_C7].desc = "MPU OFF + CORE OFF";
458 466
459 /* 467 /*
460 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot 468 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
@@ -512,6 +520,7 @@ int __init omap3_idle_init(void)
512 if (cx->type == OMAP3_STATE_C1) 520 if (cx->type == OMAP3_STATE_C1)
513 dev->safe_state = state; 521 dev->safe_state = state;
514 sprintf(state->name, "C%d", count+1); 522 sprintf(state->name, "C%d", count+1);
523 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
515 count++; 524 count++;
516 } 525 }
517 526