ARM: AM33XX: cm: Add bit-field width values

The new common clk framework includes basic definitions for mux and
divider clocks.  These definitions depend on shift and width values
instead of the pre-computed masks that the OMAP/AM33XX clk framework
has traditionally used when accessing the register to control the
mux or divisor.

To ease this transition the masks are left intact and
the width field is simply added alongside the shift and mask data.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index c1a5cab0f236..5594b42372ee 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -354,6 +354,7 @@
 
 /* AM33XX CONTROL_STATUS bitfields (partial) */
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT            22
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH            0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
 
 /* CONTROL OMAP STATUS register to identify OMAP3 features */