diff options
author | Benoit Cousson <b-cousson@ti.com> | 2011-07-10 07:56:30 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2011-07-10 07:56:30 -0400 |
commit | 11b10341bd12c87a8409c69cdcd7ee898400842f (patch) | |
tree | ec54a29bcc1ff21bdab8f39571eeb32774fb8b18 /arch/arm/mach-omap2/cminst44xx.c | |
parent | d0f0631ddc61026dca71b5b679803000d70fde50 (diff) |
OMAP: hwmod: Wait the idle status to be disabled
It is mandatory to wait for a module to be in disabled state before
potentially disabling source clock or re-asserting a reset.
omap_hwmod_idle and omap_hwmod_shutdown does not wait for
the module to be fully idle.
Add a cm_xxx accessor to wait the clkctrl idle status to be disabled.
Fix hwmod_[idle|shutdown] to use this API.
Based on Rajendra's initial patch.
Please note that most interconnects hwmod will return one timeout because
it is impossible for them to be in idle since the processor is accessing
the registers though the interconnect.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Todd Poynor <toddpoynor@google.com>
[paul@pwsan.com: move cpu_is_*() tests to the top of _wait_target_disable();
incorporate some feedback from Todd]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/cminst44xx.c')
-rw-r--r-- | arch/arm/mach-omap2/cminst44xx.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 9033dd4937c1..0fe3f147f262 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c | |||
@@ -284,3 +284,28 @@ int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, | |||
284 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | 284 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; |
285 | } | 285 | } |
286 | 286 | ||
287 | /** | ||
288 | * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled' | ||
289 | * state | ||
290 | * @part: PRCM partition ID that the CM_CLKCTRL register exists in | ||
291 | * @inst: CM instance register offset (*_INST macro) | ||
292 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
293 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
294 | * | ||
295 | * Wait for the module IDLEST to be disabled. Some PRCM transition, | ||
296 | * like reset assertion or parent clock de-activation must wait the | ||
297 | * module to be fully disabled. | ||
298 | */ | ||
299 | int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
300 | { | ||
301 | int i = 0; | ||
302 | |||
303 | if (!clkctrl_offs) | ||
304 | return 0; | ||
305 | |||
306 | omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) == | ||
307 | CLKCTRL_IDLEST_DISABLED), | ||
308 | MAX_MODULE_READY_TIME, i); | ||
309 | |||
310 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
311 | } | ||