diff options
author | Tero Kristo <t-kristo@ti.com> | 2014-10-27 11:39:24 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2014-10-27 11:39:24 -0400 |
commit | 128603f05af371acc09e4cfd9124388f1b3e2966 (patch) | |
tree | 73f6800d7fdd87c96f1ac26f3205f60d92a4347d /arch/arm/mach-omap2/cm33xx.c | |
parent | f2650d6e4fb797b436af5999ea89aa279712544b (diff) |
ARM: OMAP2+: CM: add common APIs for cm_module_enable/disable
Adds a generic CM driver API for enabling/disabling modules.
The SoC specific implementations are registered through cm_ll_data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm33xx.c')
-rw-r--r-- | arch/arm/mach-omap2/cm33xx.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index ffdcb7abf092..b9ad463a368a 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c | |||
@@ -277,13 +277,14 @@ static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, | |||
277 | /** | 277 | /** |
278 | * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL | 278 | * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL |
279 | * @mode: Module mode (SW or HW) | 279 | * @mode: Module mode (SW or HW) |
280 | * @part: CM partition, ignored for AM33xx | ||
280 | * @inst: CM instance register offset (*_INST macro) | 281 | * @inst: CM instance register offset (*_INST macro) |
281 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
282 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | 282 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) |
283 | * | 283 | * |
284 | * No return value. | 284 | * No return value. |
285 | */ | 285 | */ |
286 | void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) | 286 | static void am33xx_cm_module_enable(u8 mode, u8 part, u16 inst, |
287 | u16 clkctrl_offs) | ||
287 | { | 288 | { |
288 | u32 v; | 289 | u32 v; |
289 | 290 | ||
@@ -295,13 +296,13 @@ void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) | |||
295 | 296 | ||
296 | /** | 297 | /** |
297 | * am33xx_cm_module_disable - Disable the module inside CLKCTRL | 298 | * am33xx_cm_module_disable - Disable the module inside CLKCTRL |
299 | * @part: CM partition, ignored for AM33xx | ||
298 | * @inst: CM instance register offset (*_INST macro) | 300 | * @inst: CM instance register offset (*_INST macro) |
299 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
300 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | 301 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) |
301 | * | 302 | * |
302 | * No return value. | 303 | * No return value. |
303 | */ | 304 | */ |
304 | void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) | 305 | static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) |
305 | { | 306 | { |
306 | u32 v; | 307 | u32 v; |
307 | 308 | ||
@@ -368,6 +369,8 @@ struct clkdm_ops am33xx_clkdm_operations = { | |||
368 | static struct cm_ll_data am33xx_cm_ll_data = { | 369 | static struct cm_ll_data am33xx_cm_ll_data = { |
369 | .wait_module_ready = &am33xx_cm_wait_module_ready, | 370 | .wait_module_ready = &am33xx_cm_wait_module_ready, |
370 | .wait_module_idle = &am33xx_cm_wait_module_idle, | 371 | .wait_module_idle = &am33xx_cm_wait_module_idle, |
372 | .module_enable = &am33xx_cm_module_enable, | ||
373 | .module_disable = &am33xx_cm_module_disable, | ||
371 | }; | 374 | }; |
372 | 375 | ||
373 | int __init am33xx_cm_init(void) | 376 | int __init am33xx_cm_init(void) |