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authorPaul Walmsley <paul@pwsan.com>2011-02-25 17:39:27 -0500
committerPaul Walmsley <paul@pwsan.com>2011-03-07 22:02:13 -0500
commit92618ff8b025419960e2e845983f0f49b0cb57a9 (patch)
treeac747c8eafb7cdd6fee8399464cf79aa1b8e1f00 /arch/arm/mach-omap2/cm2xxx_3xxx.c
parent0fd0c21be71293d8a54d9075b18b5a25a1868057 (diff)
OMAP2xxx: clock: add clockfw autoidle support for APLLs
OMAP2xxx devices have two on-chip APLLs. These APLLs can automatically enter idle when not in use. Connect the APLL autoidle code to the clock code, so that the clock framework can handle this process. As part of this patch, remove the code in mach-omap2/pm24xx.c that previously handled APLL autoidle control. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm2xxx_3xxx.c')
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.c44
1 files changed, 43 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 6b0c7c85ef53..9d0dec806e92 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -25,10 +25,14 @@
25#include "cm-regbits-24xx.h" 25#include "cm-regbits-24xx.h"
26#include "cm-regbits-34xx.h" 26#include "cm-regbits-34xx.h"
27 27
28/* CM_AUTOIDLE_PLL.AUTO_* bit values */ 28/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
29#define DPLL_AUTOIDLE_DISABLE 0x0 29#define DPLL_AUTOIDLE_DISABLE 0x0
30#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3 30#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
31 31
32/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
33#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
34#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
35
32static const u8 cm_idlest_offs[] = { 36static const u8 cm_idlest_offs[] = {
33 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 37 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
34}; 38};
@@ -154,6 +158,44 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
154} 158}
155 159
156/* 160/*
161 * APLL autoidle control
162 */
163
164static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
165{
166 u32 v;
167
168 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
169 v &= ~mask;
170 v |= m << __ffs(mask);
171 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
172}
173
174void omap2xxx_cm_set_apll54_disable_autoidle(void)
175{
176 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
177 OMAP24XX_AUTO_54M_MASK);
178}
179
180void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
181{
182 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
183 OMAP24XX_AUTO_54M_MASK);
184}
185
186void omap2xxx_cm_set_apll96_disable_autoidle(void)
187{
188 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
189 OMAP24XX_AUTO_96M_MASK);
190}
191
192void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
193{
194 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
195 OMAP24XX_AUTO_96M_MASK);
196}
197
198/*
157 * 199 *
158 */ 200 */
159 201