diff options
author | Paul Walmsley <paul@pwsan.com> | 2010-12-21 23:05:15 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2010-12-21 23:05:15 -0500 |
commit | e4156ee52fe617c2c2d80b5db993ff4bf07d7c3c (patch) | |
tree | 5a2dca04df22b5eac3d5f1af4e39246ae32c5daf /arch/arm/mach-omap2/cm2_44xx.h | |
parent | b170fbe1f9f1aa38773b1bcf064ab65951ce739d (diff) |
OMAP4: CM instances: add clockdomain register offsets
In OMAP4 CM instances, some registers (CM_CLKSTCTRL, CM_STATICDEP,
CM_DYNAMICDEP, and the module-specific registers underneath) are
organized by clockdomain. Add the clockdomain offset macros to the
appropriate PRCM module header files.
This data was almost completely autogenerated from the TI hardware
database; the autogeneration scripts have been updated.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: BenoƮt Cousson <b-cousson@ti.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm2_44xx.h')
-rw-r--r-- | arch/arm/mach-omap2/cm2_44xx.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h index 0fd021069792..aa4745044065 100644 --- a/arch/arm/mach-omap2/cm2_44xx.h +++ b/arch/arm/mach-omap2/cm2_44xx.h | |||
@@ -46,6 +46,25 @@ | |||
46 | #define OMAP4430_CM2_RESTORE_INST 0x1e00 | 46 | #define OMAP4430_CM2_RESTORE_INST 0x1e00 |
47 | #define OMAP4430_CM2_INSTR_INST 0x1f00 | 47 | #define OMAP4430_CM2_INSTR_INST 0x1f00 |
48 | 48 | ||
49 | /* CM2 clockdomain register offsets (from instance start) */ | ||
50 | #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 | ||
51 | #define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 | ||
52 | #define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 | ||
53 | #define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 | ||
54 | #define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 | ||
55 | #define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 | ||
56 | #define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 | ||
57 | #define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 | ||
58 | #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 | ||
59 | #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 | ||
60 | #define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 | ||
61 | #define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 | ||
62 | #define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 | ||
63 | #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 | ||
64 | #define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 | ||
65 | #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 | ||
66 | #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 | ||
67 | |||
49 | 68 | ||
50 | /* CM2 */ | 69 | /* CM2 */ |
51 | 70 | ||