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authorRajendra Nayak <rnayak@ti.com>2009-12-08 20:24:50 -0500
committerpaul <paul@twilight.(none)>2009-12-11 19:00:45 -0500
commit9b47267f3e7f5f9b0d136c199fb8f3acb362e45e (patch)
treef7d88f1ba2cde162402deb59389ffb23a97033dd /arch/arm/mach-omap2/cm.h
parent77772d5f7dc3e329f916403ac1199615e7bab089 (diff)
ARM: OMAP4: PM: Adds CM1/2 register defs for OMAP4
This patch adds OMAP4 specific CM1 and CM2 module register defs. Autogenerated using a python scripts (gen_cm1_4430_h.py,gen_cm2_4430_h.py) developed by Paul Walmsley and Benoit Cousson. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm.h')
-rw-r--r--arch/arm/mach-omap2/cm.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index a2fcfcc253cc..e8814a60ccf7 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -4,8 +4,8 @@
4/* 4/*
5 * OMAP2/3 Clock Management (CM) register definitions 5 * OMAP2/3 Clock Management (CM) register definitions
6 * 6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation 8 * Copyright (C) 2007-2009 Nokia Corporation
9 * 9 *
10 * Written by Paul Walmsley 10 * Written by Paul Walmsley
11 * 11 *
@@ -22,6 +22,12 @@
22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) 22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
23#define OMAP34XX_CM_REGADDR(module, reg) \ 23#define OMAP34XX_CM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) 24 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
25#define OMAP44XX_CM1_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
27#define OMAP44XX_CM2_REGADDR(module, reg) \
28 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
29
30#include "cm44xx.h"
25 31
26/* 32/*
27 * Architecture-specific global CM registers 33 * Architecture-specific global CM registers
@@ -89,6 +95,7 @@
89#define OMAP3430_CM_CLKSEL2_EMU 0x0050 95#define OMAP3430_CM_CLKSEL2_EMU 0x0050
90#define OMAP3430_CM_CLKSEL3_EMU 0x0054 96#define OMAP3430_CM_CLKSEL3_EMU 0x0054
91 97
98/* CM2.CEFUSE_CM2 register offsets */
92 99
93/* Clock management domain register get/set */ 100/* Clock management domain register get/set */
94 101