diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-01-28 14:18:22 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 12:50:37 -0500 |
| commit | da0747d4faf55320f0f6cbcd8525e2a8e4619925 (patch) | |
| tree | b3fce6c33df8f555d9adbe00d679e48f9f4a81c0 /arch/arm/mach-omap2/cm-regbits-34xx.h | |
| parent | 027d8ded5d1c142eb120caff7a395c0637467ac9 (diff) | |
[ARM] OMAP2 PRCM: clean up CM_IDLEST bits
This patch fixes a few OMAP2xxx CM_IDLEST bits that were incorrectly
marked as being OMAP2xxx-wide, when they were actually 2420-specific.
Also, originally when the PRCM register macros were defined, bit shift
macros used a "_SHIFT" suffix, and mask macros used none. This became
a source of bugs and confusion, as the mask macros were mistakenly
used for shift values. Gradually, the mask macros have been updated,
piece by piece, to add a "_MASK" suffix on the end to clarify. This
patch applies this change to the CM_IDLEST_* register bits.
The patch also adds a few bits that were missing, mostly from the 3430ES1
to ES2 revisions.
linux-omap source commits are d18eff5b5fa15e170794397a6a94486d1f774f77,
e1f1a5cc24615fb790cc763c96d1c5cfe6296f5b, and part of
9fe6b6cf8d9e0cbb429fd64553a4b3160a9e99e1
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 96 |
1 files changed, 71 insertions, 25 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 844356cc75bd..6f3f5a36aae6 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -183,29 +183,52 @@ | |||
| 183 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | 183 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) |
| 184 | 184 | ||
| 185 | /* CM_IDLEST1_CORE specific bits */ | 185 | /* CM_IDLEST1_CORE specific bits */ |
| 186 | #define OMAP3430_ST_ICR (1 << 29) | 186 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 |
| 187 | #define OMAP3430_ST_AES2 (1 << 28) | 187 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) |
| 188 | #define OMAP3430_ST_SHA12 (1 << 27) | 188 | #define OMAP3430_ST_ICR_SHIFT 29 |
| 189 | #define OMAP3430_ST_DES2 (1 << 26) | 189 | #define OMAP3430_ST_ICR_MASK (1 << 29) |
| 190 | #define OMAP3430_ST_MSPRO (1 << 23) | 190 | #define OMAP3430_ST_AES2_SHIFT 28 |
| 191 | #define OMAP3430_ST_HDQ (1 << 22) | 191 | #define OMAP3430_ST_AES2_MASK (1 << 28) |
| 192 | #define OMAP3430ES1_ST_FAC (1 << 8) | 192 | #define OMAP3430_ST_SHA12_SHIFT 27 |
| 193 | #define OMAP3430ES1_ST_MAILBOXES (1 << 7) | 193 | #define OMAP3430_ST_SHA12_MASK (1 << 27) |
| 194 | #define OMAP3430_ST_OMAPCTRL (1 << 6) | 194 | #define OMAP3430_ST_DES2_SHIFT 26 |
| 195 | #define OMAP3430_ST_SDMA (1 << 2) | 195 | #define OMAP3430_ST_DES2_MASK (1 << 26) |
| 196 | #define OMAP3430_ST_SDRC (1 << 1) | 196 | #define OMAP3430_ST_MSPRO_SHIFT 23 |
| 197 | #define OMAP3430_ST_SSI (1 << 0) | 197 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) |
| 198 | #define OMAP3430_ST_HDQ_SHIFT 22 | ||
| 199 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | ||
| 200 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | ||
| 201 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | ||
| 202 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | ||
| 203 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | ||
| 204 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | ||
| 205 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | ||
| 206 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | ||
| 207 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | ||
| 208 | #define OMAP3430_ST_SDMA_SHIFT 2 | ||
| 209 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | ||
| 210 | #define OMAP3430_ST_SDRC_SHIFT 1 | ||
| 211 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | ||
| 212 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | ||
| 213 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | ||
| 198 | 214 | ||
| 199 | /* CM_IDLEST2_CORE */ | 215 | /* CM_IDLEST2_CORE */ |
| 200 | #define OMAP3430_ST_PKA (1 << 4) | 216 | #define OMAP3430_ST_PKA_SHIFT 4 |
| 201 | #define OMAP3430_ST_AES1 (1 << 3) | 217 | #define OMAP3430_ST_PKA_MASK (1 << 4) |
| 202 | #define OMAP3430_ST_RNG (1 << 2) | 218 | #define OMAP3430_ST_AES1_SHIFT 3 |
| 203 | #define OMAP3430_ST_SHA11 (1 << 1) | 219 | #define OMAP3430_ST_AES1_MASK (1 << 3) |
| 204 | #define OMAP3430_ST_DES1 (1 << 0) | 220 | #define OMAP3430_ST_RNG_SHIFT 2 |
| 221 | #define OMAP3430_ST_RNG_MASK (1 << 2) | ||
| 222 | #define OMAP3430_ST_SHA11_SHIFT 1 | ||
| 223 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | ||
| 224 | #define OMAP3430_ST_DES1_SHIFT 0 | ||
| 225 | #define OMAP3430_ST_DES1_MASK (1 << 0) | ||
| 205 | 226 | ||
| 206 | /* CM_IDLEST3_CORE */ | 227 | /* CM_IDLEST3_CORE */ |
| 207 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | 228 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 |
| 208 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | 229 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) |
| 230 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 | ||
| 231 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | ||
| 209 | 232 | ||
| 210 | /* CM_AUTOIDLE1_CORE */ | 233 | /* CM_AUTOIDLE1_CORE */ |
| 211 | #define OMAP3430ES2_AUTO_MMC3 (1 << 30) | 234 | #define OMAP3430ES2_AUTO_MMC3 (1 << 30) |
| @@ -360,6 +383,7 @@ | |||
| 360 | 383 | ||
| 361 | /* CM_FCLKEN_WKUP specific bits */ | 384 | /* CM_FCLKEN_WKUP specific bits */ |
| 362 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | 385 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 |
| 386 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) | ||
| 363 | 387 | ||
| 364 | /* CM_ICLKEN_WKUP specific bits */ | 388 | /* CM_ICLKEN_WKUP specific bits */ |
| 365 | #define OMAP3430_EN_WDT1 (1 << 4) | 389 | #define OMAP3430_EN_WDT1 (1 << 4) |
| @@ -368,11 +392,18 @@ | |||
| 368 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | 392 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
| 369 | 393 | ||
| 370 | /* CM_IDLEST_WKUP specific bits */ | 394 | /* CM_IDLEST_WKUP specific bits */ |
| 371 | #define OMAP3430_ST_WDT2 (1 << 5) | 395 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 |
| 372 | #define OMAP3430_ST_WDT1 (1 << 4) | 396 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) |
| 373 | #define OMAP3430_ST_32KSYNC (1 << 2) | 397 | #define OMAP3430_ST_WDT2_SHIFT 5 |
| 398 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | ||
| 399 | #define OMAP3430_ST_WDT1_SHIFT 4 | ||
| 400 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | ||
| 401 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | ||
| 402 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | ||
| 374 | 403 | ||
| 375 | /* CM_AUTOIDLE_WKUP */ | 404 | /* CM_AUTOIDLE_WKUP */ |
| 405 | #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) | ||
| 406 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 | ||
| 376 | #define OMAP3430_AUTO_WDT2 (1 << 5) | 407 | #define OMAP3430_AUTO_WDT2 (1 << 5) |
| 377 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | 408 | #define OMAP3430_AUTO_WDT2_SHIFT 5 |
| 378 | #define OMAP3430_AUTO_WDT1 (1 << 4) | 409 | #define OMAP3430_AUTO_WDT1 (1 << 4) |
| @@ -437,6 +468,8 @@ | |||
| 437 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | 468 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) |
| 438 | 469 | ||
| 439 | /* CM_IDLEST2_CKGEN */ | 470 | /* CM_IDLEST2_CKGEN */ |
| 471 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 | ||
| 472 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | ||
| 440 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 | 473 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 |
| 441 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | 474 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) |
| 442 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | 475 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 |
| @@ -508,7 +541,12 @@ | |||
| 508 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | 541 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
| 509 | 542 | ||
| 510 | /* CM_IDLEST_DSS */ | 543 | /* CM_IDLEST_DSS */ |
| 511 | #define OMAP3430_ST_DSS (1 << 0) | 544 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
| 545 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | ||
| 546 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | ||
| 547 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | ||
| 548 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | ||
| 549 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | ||
| 512 | 550 | ||
| 513 | /* CM_AUTOIDLE_DSS */ | 551 | /* CM_AUTOIDLE_DSS */ |
| 514 | #define OMAP3430_AUTO_DSS (1 << 0) | 552 | #define OMAP3430_AUTO_DSS (1 << 0) |
| @@ -562,10 +600,14 @@ | |||
| 562 | /* CM_ICLKEN_PER specific bits */ | 600 | /* CM_ICLKEN_PER specific bits */ |
| 563 | 601 | ||
| 564 | /* CM_IDLEST_PER */ | 602 | /* CM_IDLEST_PER */ |
| 565 | #define OMAP3430_ST_WDT3 (1 << 12) | 603 | #define OMAP3430_ST_WDT3_SHIFT 12 |
| 566 | #define OMAP3430_ST_MCBSP4 (1 << 2) | 604 | #define OMAP3430_ST_WDT3_MASK (1 << 12) |
| 567 | #define OMAP3430_ST_MCBSP3 (1 << 1) | 605 | #define OMAP3430_ST_MCBSP4_SHIFT 2 |
| 568 | #define OMAP3430_ST_MCBSP2 (1 << 0) | 606 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) |
| 607 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | ||
| 608 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | ||
| 609 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | ||
| 610 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | ||
| 569 | 611 | ||
| 570 | /* CM_AUTOIDLE_PER */ | 612 | /* CM_AUTOIDLE_PER */ |
| 571 | #define OMAP3430_AUTO_GPIO6 (1 << 17) | 613 | #define OMAP3430_AUTO_GPIO6 (1 << 17) |
| @@ -693,6 +735,10 @@ | |||
| 693 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | 735 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) |
| 694 | 736 | ||
| 695 | /* CM_IDLEST_USBHOST */ | 737 | /* CM_IDLEST_USBHOST */ |
| 738 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 | ||
| 739 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | ||
| 740 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | ||
| 741 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | ||
| 696 | 742 | ||
| 697 | /* CM_AUTOIDLE_USBHOST */ | 743 | /* CM_AUTOIDLE_USBHOST */ |
| 698 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | 744 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 |