diff options
author | Kevin Hilman <khilman@deeprootsystems.com> | 2009-04-28 18:27:44 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-05-28 13:59:07 -0400 |
commit | 8111b221a275cbc974eba26059dc764680ded9a9 (patch) | |
tree | c64ee856ffe9ff796f8a746025b82586c19e5617 /arch/arm/mach-omap2/cm-regbits-34xx.h | |
parent | ba87a9beae8b39894f55761f4aff5ae2ca624f81 (diff) |
OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init
Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework
and ensure that auto-idle bits are set for these clocks during PRCM
init.
Also add omap3_d2d_idle() function called durint PRCM setup which
ensures D2D pins are MUX'd correctly to enable retention for
standalone (no-modem) devices.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 6f3f5a36aae6..6923deb98a28 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
@@ -145,6 +145,8 @@ | |||
145 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | 145 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) |
146 | 146 | ||
147 | /* CM_FCLKEN1_CORE specific bits */ | 147 | /* CM_FCLKEN1_CORE specific bits */ |
148 | #define OMAP3430_EN_MODEM (1 << 31) | ||
149 | #define OMAP3430_EN_MODEM_SHIFT 31 | ||
148 | 150 | ||
149 | /* CM_ICLKEN1_CORE specific bits */ | 151 | /* CM_ICLKEN1_CORE specific bits */ |
150 | #define OMAP3430_EN_ICR (1 << 29) | 152 | #define OMAP3430_EN_ICR (1 << 29) |
@@ -161,6 +163,8 @@ | |||
161 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 | 163 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 |
162 | #define OMAP3430_EN_OMAPCTRL (1 << 6) | 164 | #define OMAP3430_EN_OMAPCTRL (1 << 6) |
163 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 | 165 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 |
166 | #define OMAP3430_EN_SAD2D (1 << 3) | ||
167 | #define OMAP3430_EN_SAD2D_SHIFT 3 | ||
164 | #define OMAP3430_EN_SDRC (1 << 1) | 168 | #define OMAP3430_EN_SDRC (1 << 1) |
165 | #define OMAP3430_EN_SDRC_SHIFT 1 | 169 | #define OMAP3430_EN_SDRC_SHIFT 1 |
166 | 170 | ||
@@ -176,6 +180,10 @@ | |||
176 | #define OMAP3430_EN_DES1 (1 << 0) | 180 | #define OMAP3430_EN_DES1 (1 << 0) |
177 | #define OMAP3430_EN_DES1_SHIFT 0 | 181 | #define OMAP3430_EN_DES1_SHIFT 0 |
178 | 182 | ||
183 | /* CM_ICLKEN3_CORE */ | ||
184 | #define OMAP3430_EN_MAD2D_SHIFT 3 | ||
185 | #define OMAP3430_EN_MAD2D (1 << 3) | ||
186 | |||
179 | /* CM_FCLKEN3_CORE specific bits */ | 187 | /* CM_FCLKEN3_CORE specific bits */ |
180 | #define OMAP3430ES2_EN_TS_SHIFT 1 | 188 | #define OMAP3430ES2_EN_TS_SHIFT 1 |
181 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) | 189 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) |
@@ -231,6 +239,8 @@ | |||
231 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | 239 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) |
232 | 240 | ||
233 | /* CM_AUTOIDLE1_CORE */ | 241 | /* CM_AUTOIDLE1_CORE */ |
242 | #define OMAP3430_AUTO_MODEM (1 << 31) | ||
243 | #define OMAP3430_AUTO_MODEM_SHIFT 31 | ||
234 | #define OMAP3430ES2_AUTO_MMC3 (1 << 30) | 244 | #define OMAP3430ES2_AUTO_MMC3 (1 << 30) |
235 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 | 245 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 |
236 | #define OMAP3430ES2_AUTO_ICR (1 << 29) | 246 | #define OMAP3430ES2_AUTO_ICR (1 << 29) |
@@ -287,6 +297,8 @@ | |||
287 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 | 297 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 |
288 | #define OMAP3430ES1_AUTO_D2D (1 << 3) | 298 | #define OMAP3430ES1_AUTO_D2D (1 << 3) |
289 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 | 299 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 |
300 | #define OMAP3430_AUTO_SAD2D (1 << 3) | ||
301 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 | ||
290 | #define OMAP3430_AUTO_SSI (1 << 0) | 302 | #define OMAP3430_AUTO_SSI (1 << 0) |
291 | #define OMAP3430_AUTO_SSI_SHIFT 0 | 303 | #define OMAP3430_AUTO_SSI_SHIFT 0 |
292 | 304 | ||
@@ -308,6 +320,8 @@ | |||
308 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | 320 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) |
309 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 | 321 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 |
310 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | 322 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) |
323 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 | ||
324 | #define OMAP3430_AUTO_MAD2D (1 << 3) | ||
311 | 325 | ||
312 | /* CM_CLKSEL_CORE */ | 326 | /* CM_CLKSEL_CORE */ |
313 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | 327 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 |