ARM: OMAP2: New DPLL clock framework

These changes is the result of the discussion with Paul Walmsley.
His ideas are included into this patch.

Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks,
and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk).
omap2_get_dpll_rate() now returns the correct DPLL rate, as represented
by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along
with high-frequency bypass support.

Add support for DPLLs function in locked and bypass clock modes.

Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 317040887152..9249129a5f46 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -115,6 +115,10 @@
 
 /* CM_IDLEST_PLL_MPU */
 #define OMAP3430_ST_MPU_CLK                             (1 << 0)
+#define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK_MASK                        (1 << 0)
 
 /* CM_AUTOIDLE_PLL_MPU */
 #define OMAP3430_AUTO_MPU_DPLL_SHIFT                    0