ARM: OMAP2: Clockdomain: Encode OMAP2/3 clockdomains

Add clockdomain definitions for OMAP24xx and OMAP34xx chips.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 16 insertions, 8 deletions

diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 20ac38100678..1098ecfab861 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -63,7 +63,8 @@
 #define OMAP24XX_CLKSEL_MPU_MASK                        (0x1f << 0)
 
 /* CM_CLKSTCTRL_MPU */
-#define OMAP24XX_AUTOSTATE_MPU                          (1 << 0)
+#define OMAP24XX_AUTOSTATE_MPU_SHIFT                    0
+#define OMAP24XX_AUTOSTATE_MPU_MASK                     (1 << 0)
 
 /* CM_FCLKEN1_CORE specific bits*/
 #define OMAP24XX_EN_TV_SHIFT                            2
@@ -238,9 +239,12 @@
 #define OMAP24XX_CLKSEL_GPT2_MASK                       (0x3 << 2)
 
 /* CM_CLKSTCTRL_CORE */
-#define OMAP24XX_AUTOSTATE_DSS                          (1 << 2)
-#define OMAP24XX_AUTOSTATE_L4                           (1 << 1)
-#define OMAP24XX_AUTOSTATE_L3                           (1 << 0)
+#define OMAP24XX_AUTOSTATE_DSS_SHIFT                    2
+#define OMAP24XX_AUTOSTATE_DSS_MASK                     (1 << 2)
+#define OMAP24XX_AUTOSTATE_L4_SHIFT                     1
+#define OMAP24XX_AUTOSTATE_L4_MASK                      (1 << 1)
+#define OMAP24XX_AUTOSTATE_L3_SHIFT                     0
+#define OMAP24XX_AUTOSTATE_L3_MASK                      (1 << 0)
 
 /* CM_FCLKEN_GFX */
 #define OMAP24XX_EN_3D_SHIFT                            2
@@ -255,7 +259,8 @@
 /* CM_CLKSEL_GFX specific bits */
 
 /* CM_CLKSTCTRL_GFX */
-#define OMAP24XX_AUTOSTATE_GFX                          (1 << 0)
+#define OMAP24XX_AUTOSTATE_GFX_SHIFT                    0
+#define OMAP24XX_AUTOSTATE_GFX_MASK                     (1 << 0)
 
 /* CM_FCLKEN_WKUP specific bits */
 
@@ -367,8 +372,10 @@
 #define OMAP24XX_CLKSEL_DSP_MASK                        (0x1f << 0)
 
 /* CM_CLKSTCTRL_DSP */
-#define OMAP2420_AUTOSTATE_IVA                          (1 << 8)
-#define OMAP24XX_AUTOSTATE_DSP                          (1 << 0)
+#define OMAP2420_AUTOSTATE_IVA_SHIFT                    8
+#define OMAP2420_AUTOSTATE_IVA_MASK                     (1 << 8)
+#define OMAP24XX_AUTOSTATE_DSP_SHIFT                    0
+#define OMAP24XX_AUTOSTATE_DSP_MASK                     (1 << 0)
 
 /* CM_FCLKEN_MDM */
 /* 2430 only */
@@ -396,6 +403,7 @@
 
 /* CM_CLKSTCTRL_MDM */
 /* 2430 only */
-#define OMAP2430_AUTOSTATE_MDM                          (1 << 0)
+#define OMAP2430_AUTOSTATE_MDM_SHIFT                    0
+#define OMAP2430_AUTOSTATE_MDM_MASK                     (1 << 0)
 
 #endif