aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/clockdomains44xx.h
diff options
context:
space:
mode:
authorAbhijit Pagare <abhijitpagare@ti.com>2010-01-26 22:12:54 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-26 22:12:54 -0500
commit30b8863d2aa9d3f4804302f98821732a6a8f1419 (patch)
treea48c6576f7abf8dbed00c98bfec91ec8bf08ed20 /arch/arm/mach-omap2/clockdomains44xx.h
parentb099474aa4e7fbaf5dc3b5858bc83dee2f94c60f (diff)
ARM: OMAP4: PM: Add the Autogenerated OMAP4 specific clock domain framework.
The Autogenerated OMAP4 clock domain specific file (mach-omap2/clockdomains44xx.h) is added here. This file is auto-generated using python scripting, and following is the lsit of the people involved: Benoit Cousson Abhijit Pagare Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clockdomains44xx.h')
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx.h237
1 files changed, 237 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h
new file mode 100644
index 000000000000..2f23d3830ede
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains44xx.h
@@ -0,0 +1,237 @@
1/*
2 * OMAP4 Clock domains framework
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
22#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
23
24#include <plat/clockdomain.h>
25
26#if defined(CONFIG_ARCH_OMAP4)
27
28static struct clockdomain l4_cefuse_44xx_clkdm = {
29 .name = "l4_cefuse_clkdm",
30 .pwrdm = { .name = "cefuse_pwrdm" },
31 .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL,
32 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
33 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
34 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
35};
36
37static struct clockdomain l4_cfg_44xx_clkdm = {
38 .name = "l4_cfg_clkdm",
39 .pwrdm = { .name = "core_pwrdm" },
40 .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL,
41 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
42 .flags = CLKDM_CAN_HWSUP,
43 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
44};
45
46static struct clockdomain tesla_44xx_clkdm = {
47 .name = "tesla_clkdm",
48 .pwrdm = { .name = "tesla_pwrdm" },
49 .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL,
50 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
51 .flags = CLKDM_CAN_HWSUP_SWSUP,
52 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
53};
54
55static struct clockdomain l3_gfx_44xx_clkdm = {
56 .name = "l3_gfx_clkdm",
57 .pwrdm = { .name = "gfx_pwrdm" },
58 .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL,
59 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
60 .flags = CLKDM_CAN_HWSUP_SWSUP,
61 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
62};
63
64static struct clockdomain ivahd_44xx_clkdm = {
65 .name = "ivahd_clkdm",
66 .pwrdm = { .name = "ivahd_pwrdm" },
67 .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL,
68 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
69 .flags = CLKDM_CAN_HWSUP_SWSUP,
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
71};
72
73static struct clockdomain l4_secure_44xx_clkdm = {
74 .name = "l4_secure_clkdm",
75 .pwrdm = { .name = "l4per_pwrdm" },
76 .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL,
77 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
78 .flags = CLKDM_CAN_HWSUP_SWSUP,
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
80};
81
82static struct clockdomain l4_per_44xx_clkdm = {
83 .name = "l4_per_clkdm",
84 .pwrdm = { .name = "l4per_pwrdm" },
85 .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL,
86 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
87 .flags = CLKDM_CAN_HWSUP_SWSUP,
88 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
89};
90
91static struct clockdomain abe_44xx_clkdm = {
92 .name = "abe_clkdm",
93 .pwrdm = { .name = "abe_pwrdm" },
94 .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL,
95 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
96 .flags = CLKDM_CAN_HWSUP_SWSUP,
97 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
98};
99
100static struct clockdomain l3_init_44xx_clkdm = {
101 .name = "l3_init_clkdm",
102 .pwrdm = { .name = "l3init_pwrdm" },
103 .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL,
104 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
105 .flags = CLKDM_CAN_HWSUP_SWSUP,
106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
107};
108
109static struct clockdomain mpuss_44xx_clkdm = {
110 .name = "mpuss_clkdm",
111 .pwrdm = { .name = "mpu_pwrdm" },
112 .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL,
113 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
114 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
115 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
116};
117
118static struct clockdomain mpu0_44xx_clkdm = {
119 .name = "mpu0_clkdm",
120 .pwrdm = { .name = "cpu0_pwrdm" },
121 .clkstctrl_reg = OMAP4430_CM_PDA_CPU0_CLKSTCTRL,
122 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
123 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
124 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
125};
126
127static struct clockdomain mpu1_44xx_clkdm = {
128 .name = "mpu1_clkdm",
129 .pwrdm = { .name = "cpu1_pwrdm" },
130 .clkstctrl_reg = OMAP4430_CM_PDA_CPU1_CLKSTCTRL,
131 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
132 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
134};
135
136static struct clockdomain l3_emif_44xx_clkdm = {
137 .name = "l3_emif_clkdm",
138 .pwrdm = { .name = "core_pwrdm" },
139 .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL,
140 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
141 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
143};
144
145static struct clockdomain l4_ao_44xx_clkdm = {
146 .name = "l4_ao_clkdm",
147 .pwrdm = { .name = "always_on_core_pwrdm" },
148 .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL,
149 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
150 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
151 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
152};
153
154static struct clockdomain ducati_44xx_clkdm = {
155 .name = "ducati_clkdm",
156 .pwrdm = { .name = "core_pwrdm" },
157 .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL,
158 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
159 .flags = CLKDM_CAN_HWSUP_SWSUP,
160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
161};
162
163static struct clockdomain l3_2_44xx_clkdm = {
164 .name = "l3_2_clkdm",
165 .pwrdm = { .name = "core_pwrdm" },
166 .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL,
167 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
168 .flags = CLKDM_CAN_HWSUP,
169 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
170};
171
172static struct clockdomain l3_1_44xx_clkdm = {
173 .name = "l3_1_clkdm",
174 .pwrdm = { .name = "core_pwrdm" },
175 .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL,
176 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
177 .flags = CLKDM_CAN_HWSUP,
178 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
179};
180
181static struct clockdomain l3_d2d_44xx_clkdm = {
182 .name = "l3_d2d_clkdm",
183 .pwrdm = { .name = "core_pwrdm" },
184 .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL,
185 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
186 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
187 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
188};
189
190static struct clockdomain iss_44xx_clkdm = {
191 .name = "iss_clkdm",
192 .pwrdm = { .name = "cam_pwrdm" },
193 .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL,
194 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
195 .flags = CLKDM_CAN_HWSUP_SWSUP,
196 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
197};
198
199static struct clockdomain l3_dss_44xx_clkdm = {
200 .name = "l3_dss_clkdm",
201 .pwrdm = { .name = "dss_pwrdm" },
202 .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL,
203 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
204 .flags = CLKDM_CAN_HWSUP_SWSUP,
205 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
206};
207
208static struct clockdomain l4_wkup_44xx_clkdm = {
209 .name = "l4_wkup_clkdm",
210 .pwrdm = { .name = "wkup_pwrdm" },
211 .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL,
212 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
213 .flags = CLKDM_CAN_HWSUP,
214 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
215};
216
217static struct clockdomain emu_sys_44xx_clkdm = {
218 .name = "emu_sys_clkdm",
219 .pwrdm = { .name = "emu_pwrdm" },
220 .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL,
221 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
222 .flags = CLKDM_CAN_HWSUP,
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
224};
225
226static struct clockdomain l3_dma_44xx_clkdm = {
227 .name = "l3_dma_clkdm",
228 .pwrdm = { .name = "core_pwrdm" },
229 .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL,
230 .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
231 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
232 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
233};
234
235#endif
236
237#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 23:29:27 -0500