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authorPaul Walmsley <paul@pwsan.com>2010-01-26 22:12:59 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-26 22:12:59 -0500
commita26017002847eef09625a94f897a0fb1ff58da4b (patch)
tree76cfe961ab11fa6972915109d3adee5ec723b5c2 /arch/arm/mach-omap2/clockdomains.h
parent55ed96945b1f3d0f4ad21a27b32ce4bd99d8c268 (diff)
OMAP2/3 clockdomains: split shared structures so usecounting works
Previously some of the clockdomain wakeup/sleep dependency structures were shared between several domains. For the subsequent wakeup and sleep dependency usecounting patch to work, these can no longer be shared. This patch splits the shared structures apart. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clockdomains.h')
-rw-r--r--arch/arm/mach-omap2/clockdomains.h163
1 files changed, 127 insertions, 36 deletions
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index ff216f24f1a0..9629ef1c7535 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -52,6 +52,8 @@
52 * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP 52 * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
53 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE 53 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
54 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE 54 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
55 * These can share data since they will never be present simultaneously
56 * on the same device.
55 */ 57 */
56static struct clkdm_dep gfx_sgx_wkdeps[] = { 58static struct clkdm_dep gfx_sgx_wkdeps[] = {
57 { 59 {
@@ -86,11 +88,32 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = {
86 88
87/* Wakeup dependency source arrays */ 89/* Wakeup dependency source arrays */
88 90
91/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
92static struct clkdm_dep dsp_24xx_wkdeps[] = {
93 {
94 .clkdm_name = "core_l3_clkdm",
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
96 },
97 {
98 .clkdm_name = "core_l4_clkdm",
99 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
100 },
101 {
102 .clkdm_name = "mpu_clkdm",
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
104 },
105 {
106 .clkdm_name = "wkup_clkdm",
107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
108 },
109 { NULL },
110};
111
89/* 112/*
90 * 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP 113 * 2420/2430 PM_WKDEP_MDM: CORE, MPU, WKUP
91 * 2420/2430 PM_WKDEP_MDM: same as DSP 114 * XXX This is probably 2430-only; 2420 did not have a stacked modem config.
92 */ 115 */
93static struct clkdm_dep dsp_mdm_24xx_wkdeps[] = { 116static struct clkdm_dep mdm_24xx_wkdeps[] = {
94 { 117 {
95 .clkdm_name = "core_l3_clkdm", 118 .clkdm_name = "core_l3_clkdm",
96 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX) 119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
@@ -172,11 +195,8 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
172 195
173#ifdef CONFIG_ARCH_OMAP34XX 196#ifdef CONFIG_ARCH_OMAP34XX
174 197
175/* 198/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
176 * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP 199static struct clkdm_dep per_wkdeps[] = {
177 * (USBHOST is ES2 only)
178 */
179static struct clkdm_dep per_usbhost_wkdeps[] = {
180 { 200 {
181 .clkdm_name = "core_l3_clkdm", 201 .clkdm_name = "core_l3_clkdm",
182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 202 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
@@ -200,9 +220,32 @@ static struct clkdm_dep per_usbhost_wkdeps[] = {
200 { NULL }, 220 { NULL },
201}; 221};
202 222
203/* 223/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
204 * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER 224static struct clkdm_dep usbhost_wkdeps[] = {
205 */ 225 {
226 .clkdm_name = "core_l3_clkdm",
227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
228 },
229 {
230 .clkdm_name = "core_l4_clkdm",
231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
232 },
233 {
234 .clkdm_name = "iva2_clkdm",
235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
236 },
237 {
238 .clkdm_name = "mpu_clkdm",
239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
240 },
241 {
242 .clkdm_name = "wkup_clkdm",
243 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
244 },
245 { NULL },
246};
247
248/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
206static struct clkdm_dep mpu_34xx_wkdeps[] = { 249static struct clkdm_dep mpu_34xx_wkdeps[] = {
207 { 250 {
208 .clkdm_name = "core_l3_clkdm", 251 .clkdm_name = "core_l3_clkdm",
@@ -227,9 +270,7 @@ static struct clkdm_dep mpu_34xx_wkdeps[] = {
227 { NULL }, 270 { NULL },
228}; 271};
229 272
230/* 273/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
231 * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
232 */
233static struct clkdm_dep iva2_wkdeps[] = { 274static struct clkdm_dep iva2_wkdeps[] = {
234 { 275 {
235 .clkdm_name = "core_l3_clkdm", 276 .clkdm_name = "core_l3_clkdm",
@@ -259,8 +300,25 @@ static struct clkdm_dep iva2_wkdeps[] = {
259}; 300};
260 301
261 302
262/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */ 303/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
263static struct clkdm_dep cam_dss_wkdeps[] = { 304static struct clkdm_dep cam_wkdeps[] = {
305 {
306 .clkdm_name = "iva2_clkdm",
307 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
308 },
309 {
310 .clkdm_name = "mpu_clkdm",
311 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
312 },
313 {
314 .clkdm_name = "wkup_clkdm",
315 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
316 },
317 { NULL },
318};
319
320/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
321static struct clkdm_dep dss_wkdeps[] = {
264 { 322 {
265 .clkdm_name = "iva2_clkdm", 323 .clkdm_name = "iva2_clkdm",
266 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 324 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
@@ -288,11 +346,8 @@ static struct clkdm_dep neon_wkdeps[] = {
288 346
289/* Sleep dependency source arrays for 34xx-specific clkdms - 34XX only */ 347/* Sleep dependency source arrays for 34xx-specific clkdms - 34XX only */
290 348
291/* 349/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
292 * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA 350static struct clkdm_dep dss_sleepdeps[] = {
293 * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
294 */
295static struct clkdm_dep dss_per_usbhost_sleepdeps[] = {
296 { 351 {
297 .clkdm_name = "mpu_clkdm", 352 .clkdm_name = "mpu_clkdm",
298 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 353 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
@@ -304,12 +359,48 @@ static struct clkdm_dep dss_per_usbhost_sleepdeps[] = {
304 { NULL }, 359 { NULL },
305}; 360};
306 361
362/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
363static struct clkdm_dep per_sleepdeps[] = {
364 {
365 .clkdm_name = "mpu_clkdm",
366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
367 },
368 {
369 .clkdm_name = "iva2_clkdm",
370 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
371 },
372 { NULL },
373};
374
375/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
376static struct clkdm_dep usbhost_sleepdeps[] = {
377 {
378 .clkdm_name = "mpu_clkdm",
379 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
380 },
381 {
382 .clkdm_name = "iva2_clkdm",
383 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
384 },
385 { NULL },
386};
387
388/* 3430: CM_SLEEPDEP_CAM: MPU */
389static struct clkdm_dep cam_sleepdeps[] = {
390 {
391 .clkdm_name = "mpu_clkdm",
392 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
393 },
394 { NULL },
395};
396
307/* 397/*
308 * 3430: CM_SLEEPDEP_CAM: MPU
309 * 3430ES1: CM_SLEEPDEP_GFX: MPU 398 * 3430ES1: CM_SLEEPDEP_GFX: MPU
310 * 3430ES2: CM_SLEEPDEP_SGX: MPU 399 * 3430ES2: CM_SLEEPDEP_SGX: MPU
400 * These can share data since they will never be present simultaneously
401 * on the same device.
311 */ 402 */
312static struct clkdm_dep cam_gfx_sleepdeps[] = { 403static struct clkdm_dep gfx_sgx_sleepdeps[] = {
313 { 404 {
314 .clkdm_name = "mpu_clkdm", 405 .clkdm_name = "mpu_clkdm",
315 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 406 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
@@ -376,7 +467,7 @@ static struct clockdomain iva1_2420_clkdm = {
376 .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, 467 .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
377 OMAP2_CM_CLKSTCTRL), 468 OMAP2_CM_CLKSTCTRL),
378 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, 469 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
379 .wkdep_srcs = dsp_mdm_24xx_wkdeps, 470 .wkdep_srcs = dsp_24xx_wkdeps,
380 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, 471 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
381 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 472 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
382}; 473};
@@ -458,7 +549,7 @@ static struct clockdomain mdm_clkdm = {
458 .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD, 549 .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
459 OMAP2_CM_CLKSTCTRL), 550 OMAP2_CM_CLKSTCTRL),
460 .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, 551 .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
461 .wkdep_srcs = dsp_mdm_24xx_wkdeps, 552 .wkdep_srcs = mdm_24xx_wkdeps,
462 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, 553 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
463 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 554 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
464}; 555};
@@ -470,7 +561,7 @@ static struct clockdomain dsp_2430_clkdm = {
470 .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD, 561 .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
471 OMAP2_CM_CLKSTCTRL), 562 OMAP2_CM_CLKSTCTRL),
472 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, 563 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
473 .wkdep_srcs = dsp_mdm_24xx_wkdeps, 564 .wkdep_srcs = dsp_24xx_wkdeps,
474 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, 565 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
475 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 566 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
476}; 567};
@@ -575,7 +666,7 @@ static struct clockdomain gfx_3430es1_clkdm = {
575 .flags = CLKDM_CAN_HWSUP_SWSUP, 666 .flags = CLKDM_CAN_HWSUP_SWSUP,
576 .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), 667 .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
577 .wkdep_srcs = gfx_sgx_wkdeps, 668 .wkdep_srcs = gfx_sgx_wkdeps,
578 .sleepdep_srcs = cam_gfx_sleepdeps, 669 .sleepdep_srcs = gfx_sgx_sleepdeps,
579 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, 670 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), 671 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
581}; 672};
@@ -587,7 +678,7 @@ static struct clockdomain sgx_clkdm = {
587 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, 678 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
588 OMAP2_CM_CLKSTCTRL), 679 OMAP2_CM_CLKSTCTRL),
589 .wkdep_srcs = gfx_sgx_wkdeps, 680 .wkdep_srcs = gfx_sgx_wkdeps,
590 .sleepdep_srcs = cam_gfx_sleepdeps, 681 .sleepdep_srcs = gfx_sgx_sleepdeps,
591 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, 682 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
592 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 683 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
593}; 684};
@@ -646,8 +737,8 @@ static struct clockdomain dss_34xx_clkdm = {
646 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 737 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
647 OMAP2_CM_CLKSTCTRL), 738 OMAP2_CM_CLKSTCTRL),
648 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, 739 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
649 .wkdep_srcs = cam_dss_wkdeps, 740 .wkdep_srcs = dss_wkdeps,
650 .sleepdep_srcs = dss_per_usbhost_sleepdeps, 741 .sleepdep_srcs = dss_sleepdeps,
651 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, 742 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
652 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 743 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
653}; 744};
@@ -658,8 +749,8 @@ static struct clockdomain cam_clkdm = {
658 .flags = CLKDM_CAN_HWSUP_SWSUP, 749 .flags = CLKDM_CAN_HWSUP_SWSUP,
659 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, 750 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
660 OMAP2_CM_CLKSTCTRL), 751 OMAP2_CM_CLKSTCTRL),
661 .wkdep_srcs = cam_dss_wkdeps, 752 .wkdep_srcs = cam_wkdeps,
662 .sleepdep_srcs = cam_gfx_sleepdeps, 753 .sleepdep_srcs = cam_sleepdeps,
663 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, 754 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
664 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 755 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
665}; 756};
@@ -670,8 +761,8 @@ static struct clockdomain usbhost_clkdm = {
670 .flags = CLKDM_CAN_HWSUP_SWSUP, 761 .flags = CLKDM_CAN_HWSUP_SWSUP,
671 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, 762 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
672 OMAP2_CM_CLKSTCTRL), 763 OMAP2_CM_CLKSTCTRL),
673 .wkdep_srcs = per_usbhost_wkdeps, 764 .wkdep_srcs = usbhost_wkdeps,
674 .sleepdep_srcs = dss_per_usbhost_sleepdeps, 765 .sleepdep_srcs = usbhost_sleepdeps,
675 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, 766 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
676 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 767 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
677}; 768};
@@ -683,8 +774,8 @@ static struct clockdomain per_clkdm = {
683 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, 774 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
684 OMAP2_CM_CLKSTCTRL), 775 OMAP2_CM_CLKSTCTRL),
685 .dep_bit = OMAP3430_EN_PER_SHIFT, 776 .dep_bit = OMAP3430_EN_PER_SHIFT,
686 .wkdep_srcs = per_usbhost_wkdeps, 777 .wkdep_srcs = per_wkdeps,
687 .sleepdep_srcs = dss_per_usbhost_sleepdeps, 778 .sleepdep_srcs = per_sleepdeps,
688 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, 779 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
689 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 780 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
690}; 781};