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authorPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:15 -0500
committerPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:15 -0500
commitbd2122ca358fbd5c8e94869ae731a0951b36c757 (patch)
treec94a8080157eaaf52880187bbe5ce31fabb7161f /arch/arm/mach-omap2/clockdomain.c
parente4156ee52fe617c2c2d80b5db993ff4bf07d7c3c (diff)
OMAP4: clockdomains: add OMAP4 PRCM data and OMAP4 support
Add PRCM partition, CM instance register address offset, and clockdomain register address offset to each OMAP4 struct clockdomain record. Add OMAP4 clockdomain code to use this new data to access registers properly. While here, clean up some nearby clockdomain code to allocate auto variables in my recollection of Linus's preferred style. The autogeneration scripts have been updated. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: BenoƮt Cousson <b-cousson@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clockdomain.c')
-rw-r--r--arch/arm/mach-omap2/clockdomain.c75
1 files changed, 57 insertions, 18 deletions
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 8e3276bfed25..555a518836b9 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -29,6 +29,9 @@
29#include "prm2xxx_3xxx.h" 29#include "prm2xxx_3xxx.h"
30#include "prm-regbits-24xx.h" 30#include "prm-regbits-24xx.h"
31#include "cm2xxx_3xxx.h" 31#include "cm2xxx_3xxx.h"
32#include "cm-regbits-34xx.h"
33#include "cminst44xx.h"
34#include "prcm44xx.h"
32 35
33#include <plat/clock.h> 36#include <plat/clock.h>
34#include <plat/powerdomain.h> 37#include <plat/powerdomain.h>
@@ -247,13 +250,21 @@ static void _enable_hwsup(struct clockdomain *clkdm)
247 250
248 if (cpu_is_omap24xx()) 251 if (cpu_is_omap24xx())
249 bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; 252 bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
250 else if (cpu_is_omap34xx() || cpu_is_omap44xx()) 253 else if (cpu_is_omap34xx())
251 bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; 254 bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
255 else if (cpu_is_omap44xx())
256 return omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
257 clkdm->cm_inst,
258 clkdm->clkdm_offs);
252 else 259 else
253 BUG(); 260 BUG();
254 261
255 bits = bits << __ffs(clkdm->clktrctrl_mask); 262 bits = bits << __ffs(clkdm->clktrctrl_mask);
256 263
264 /*
265 * XXX clkstctrl_reg is known on OMAP2 - this clkdm
266 * field is not needed
267 */
257 v = __raw_readl(clkdm->clkstctrl_reg); 268 v = __raw_readl(clkdm->clkstctrl_reg);
258 v &= ~(clkdm->clktrctrl_mask); 269 v &= ~(clkdm->clktrctrl_mask);
259 v |= bits; 270 v |= bits;
@@ -275,21 +286,27 @@ static void _disable_hwsup(struct clockdomain *clkdm)
275{ 286{
276 u32 bits, v; 287 u32 bits, v;
277 288
278 if (cpu_is_omap24xx()) { 289 if (cpu_is_omap24xx())
279 bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; 290 bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
280 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 291 else if (cpu_is_omap34xx())
281 bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; 292 bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
282 } else { 293 else if (cpu_is_omap44xx())
294 return omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
295 clkdm->cm_inst,
296 clkdm->clkdm_offs);
297 else
283 BUG(); 298 BUG();
284 }
285 299
286 bits = bits << __ffs(clkdm->clktrctrl_mask); 300 bits = bits << __ffs(clkdm->clktrctrl_mask);
287 301
302 /*
303 * XXX clkstctrl_reg is known on OMAP2 - this clkdm
304 * field is not needed
305 */
288 v = __raw_readl(clkdm->clkstctrl_reg); 306 v = __raw_readl(clkdm->clkstctrl_reg);
289 v &= ~(clkdm->clktrctrl_mask); 307 v &= ~(clkdm->clktrctrl_mask);
290 v |= bits; 308 v |= bits;
291 __raw_writel(v, clkdm->clkstctrl_reg); 309 __raw_writel(v, clkdm->clkstctrl_reg);
292
293} 310}
294 311
295/* Public functions */ 312/* Public functions */
@@ -727,14 +744,20 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
727 */ 744 */
728static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) 745static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
729{ 746{
730 u32 v; 747 u32 v = 0;
731 748
732 if (!clkdm) 749 if (!clkdm)
733 return -EINVAL; 750 return -EINVAL;
734 751
735 v = __raw_readl(clkdm->clkstctrl_reg); 752 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
736 v &= clkdm->clktrctrl_mask; 753 v = __raw_readl(clkdm->clkstctrl_reg);
737 v >>= __ffs(clkdm->clktrctrl_mask); 754 v &= clkdm->clktrctrl_mask;
755 v >>= __ffs(clkdm->clktrctrl_mask);
756 } else if (cpu_is_omap44xx()) {
757 pr_warn("OMAP4 clockdomain: missing wakeup/sleep deps\n");
758 } else {
759 BUG();
760 }
738 761
739 return v; 762 return v;
740} 763}
@@ -750,6 +773,8 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
750 */ 773 */
751int omap2_clkdm_sleep(struct clockdomain *clkdm) 774int omap2_clkdm_sleep(struct clockdomain *clkdm)
752{ 775{
776 u32 bits, v;
777
753 if (!clkdm) 778 if (!clkdm)
754 return -EINVAL; 779 return -EINVAL;
755 780
@@ -766,16 +791,22 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
766 omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, 791 omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
767 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 792 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
768 793
769 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 794 } else if (cpu_is_omap34xx()) {
770 795
771 u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << 796 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
772 __ffs(clkdm->clktrctrl_mask)); 797 __ffs(clkdm->clktrctrl_mask));
773 798
774 u32 v = __raw_readl(clkdm->clkstctrl_reg); 799 v = __raw_readl(clkdm->clkstctrl_reg);
775 v &= ~(clkdm->clktrctrl_mask); 800 v &= ~(clkdm->clktrctrl_mask);
776 v |= bits; 801 v |= bits;
777 __raw_writel(v, clkdm->clkstctrl_reg); 802 __raw_writel(v, clkdm->clkstctrl_reg);
778 803
804 } else if (cpu_is_omap44xx()) {
805
806 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
807 clkdm->cm_inst,
808 clkdm->clkdm_offs);
809
779 } else { 810 } else {
780 BUG(); 811 BUG();
781 }; 812 };
@@ -794,6 +825,8 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
794 */ 825 */
795int omap2_clkdm_wakeup(struct clockdomain *clkdm) 826int omap2_clkdm_wakeup(struct clockdomain *clkdm)
796{ 827{
828 u32 bits, v;
829
797 if (!clkdm) 830 if (!clkdm)
798 return -EINVAL; 831 return -EINVAL;
799 832
@@ -810,16 +843,22 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
810 omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, 843 omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
811 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 844 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
812 845
813 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 846 } else if (cpu_is_omap34xx()) {
814 847
815 u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << 848 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
816 __ffs(clkdm->clktrctrl_mask)); 849 __ffs(clkdm->clktrctrl_mask));
817 850
818 u32 v = __raw_readl(clkdm->clkstctrl_reg); 851 v = __raw_readl(clkdm->clkstctrl_reg);
819 v &= ~(clkdm->clktrctrl_mask); 852 v &= ~(clkdm->clktrctrl_mask);
820 v |= bits; 853 v |= bits;
821 __raw_writel(v, clkdm->clkstctrl_reg); 854 __raw_writel(v, clkdm->clkstctrl_reg);
822 855
856 } else if (cpu_is_omap44xx()) {
857
858 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
859 clkdm->cm_inst,
860 clkdm->clkdm_offs);
861
823 } else { 862 } else {
824 BUG(); 863 BUG();
825 }; 864 };