diff options
| author | Tony Lindgren <tony@atomide.com> | 2010-02-15 12:27:25 -0500 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2010-02-15 12:27:25 -0500 |
| commit | 4751227df948582e82f19df30efa662ab71fa980 (patch) | |
| tree | fcaa71e589feedf607377881109088b6eba50822 /arch/arm/mach-omap2/clock44xx_data.c | |
| parent | 61a07c80a7cf7333475e7eda9934dac9a8a9c8b9 (diff) | |
omap3/4: Fix compile for multi-omap for clkops_noncore_dpll_ops
Rename clkops_noncore_dpll_ops for omap3 and omap4.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock44xx_data.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 35ffe638def8..86af31d80a34 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c | |||
| @@ -279,7 +279,7 @@ static struct clk dpll_abe_ck = { | |||
| 279 | .parent = &abe_dpll_refclk_mux_ck, | 279 | .parent = &abe_dpll_refclk_mux_ck, |
| 280 | .dpll_data = &dpll_abe_dd, | 280 | .dpll_data = &dpll_abe_dd, |
| 281 | .init = &omap2_init_dpll_parent, | 281 | .init = &omap2_init_dpll_parent, |
| 282 | .ops = &clkops_noncore_dpll_ops, | 282 | .ops = &omap4_clkops_noncore_dpll_ops, |
| 283 | .recalc = &omap3_dpll_recalc, | 283 | .recalc = &omap3_dpll_recalc, |
| 284 | .round_rate = &omap2_dpll_round_rate, | 284 | .round_rate = &omap2_dpll_round_rate, |
| 285 | .set_rate = &omap3_noncore_dpll_set_rate, | 285 | .set_rate = &omap3_noncore_dpll_set_rate, |
| @@ -668,7 +668,7 @@ static struct clk dpll_iva_ck = { | |||
| 668 | .parent = &dpll_sys_ref_clk, | 668 | .parent = &dpll_sys_ref_clk, |
| 669 | .dpll_data = &dpll_iva_dd, | 669 | .dpll_data = &dpll_iva_dd, |
| 670 | .init = &omap2_init_dpll_parent, | 670 | .init = &omap2_init_dpll_parent, |
| 671 | .ops = &clkops_noncore_dpll_ops, | 671 | .ops = &omap4_clkops_noncore_dpll_ops, |
| 672 | .recalc = &omap3_dpll_recalc, | 672 | .recalc = &omap3_dpll_recalc, |
| 673 | .round_rate = &omap2_dpll_round_rate, | 673 | .round_rate = &omap2_dpll_round_rate, |
| 674 | .set_rate = &omap3_noncore_dpll_set_rate, | 674 | .set_rate = &omap3_noncore_dpll_set_rate, |
| @@ -731,7 +731,7 @@ static struct clk dpll_mpu_ck = { | |||
| 731 | .parent = &dpll_sys_ref_clk, | 731 | .parent = &dpll_sys_ref_clk, |
| 732 | .dpll_data = &dpll_mpu_dd, | 732 | .dpll_data = &dpll_mpu_dd, |
| 733 | .init = &omap2_init_dpll_parent, | 733 | .init = &omap2_init_dpll_parent, |
| 734 | .ops = &clkops_noncore_dpll_ops, | 734 | .ops = &omap4_clkops_noncore_dpll_ops, |
| 735 | .recalc = &omap3_dpll_recalc, | 735 | .recalc = &omap3_dpll_recalc, |
| 736 | .round_rate = &omap2_dpll_round_rate, | 736 | .round_rate = &omap2_dpll_round_rate, |
| 737 | .set_rate = &omap3_noncore_dpll_set_rate, | 737 | .set_rate = &omap3_noncore_dpll_set_rate, |
| @@ -807,7 +807,7 @@ static struct clk dpll_per_ck = { | |||
| 807 | .parent = &dpll_sys_ref_clk, | 807 | .parent = &dpll_sys_ref_clk, |
| 808 | .dpll_data = &dpll_per_dd, | 808 | .dpll_data = &dpll_per_dd, |
| 809 | .init = &omap2_init_dpll_parent, | 809 | .init = &omap2_init_dpll_parent, |
| 810 | .ops = &clkops_noncore_dpll_ops, | 810 | .ops = &omap4_clkops_noncore_dpll_ops, |
| 811 | .recalc = &omap3_dpll_recalc, | 811 | .recalc = &omap3_dpll_recalc, |
| 812 | .round_rate = &omap2_dpll_round_rate, | 812 | .round_rate = &omap2_dpll_round_rate, |
| 813 | .set_rate = &omap3_noncore_dpll_set_rate, | 813 | .set_rate = &omap3_noncore_dpll_set_rate, |
| @@ -930,7 +930,7 @@ static struct clk dpll_unipro_ck = { | |||
| 930 | .parent = &dpll_sys_ref_clk, | 930 | .parent = &dpll_sys_ref_clk, |
| 931 | .dpll_data = &dpll_unipro_dd, | 931 | .dpll_data = &dpll_unipro_dd, |
| 932 | .init = &omap2_init_dpll_parent, | 932 | .init = &omap2_init_dpll_parent, |
| 933 | .ops = &clkops_noncore_dpll_ops, | 933 | .ops = &omap4_clkops_noncore_dpll_ops, |
| 934 | .recalc = &omap3_dpll_recalc, | 934 | .recalc = &omap3_dpll_recalc, |
| 935 | .round_rate = &omap2_dpll_round_rate, | 935 | .round_rate = &omap2_dpll_round_rate, |
| 936 | .set_rate = &omap3_noncore_dpll_set_rate, | 936 | .set_rate = &omap3_noncore_dpll_set_rate, |
| @@ -988,7 +988,7 @@ static struct clk dpll_usb_ck = { | |||
| 988 | .parent = &dpll_sys_ref_clk, | 988 | .parent = &dpll_sys_ref_clk, |
| 989 | .dpll_data = &dpll_usb_dd, | 989 | .dpll_data = &dpll_usb_dd, |
| 990 | .init = &omap2_init_dpll_parent, | 990 | .init = &omap2_init_dpll_parent, |
| 991 | .ops = &clkops_noncore_dpll_ops, | 991 | .ops = &omap4_clkops_noncore_dpll_ops, |
| 992 | .recalc = &omap3_dpll_recalc, | 992 | .recalc = &omap3_dpll_recalc, |
| 993 | .round_rate = &omap2_dpll_round_rate, | 993 | .round_rate = &omap2_dpll_round_rate, |
| 994 | .set_rate = &omap3_noncore_dpll_set_rate, | 994 | .set_rate = &omap3_noncore_dpll_set_rate, |