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authorJon Hunter <jon-hunter@ti.com>2011-07-09 21:14:47 -0400
committerPaul Walmsley <paul@pwsan.com>2011-07-09 22:00:14 -0400
commitde474535763c1a5c50cb26f34ec60f10aebc53fe (patch)
treed19581ae0b56a160935c53d307d99f594c650355 /arch/arm/mach-omap2/clock44xx_data.c
parent628479a8ea5d32ef26ba0b4eb26f8d6712a574ec (diff)
OMAP4: clock data: Remove McASP2, McASP3 and MMC6 clocks
McASP2, 3 and MMC6 modules are not present in the OMAP4 family. Remove the fclk and the clksel related to these nodes. Rename the references that were potentially re-used in order nodes. Remove related macros in prcm header files. Update TI copyright date. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [b-cousson@ti.com: Update the patch according to autogen output] Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split PRCM data changes into a separate patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c86
1 files changed, 31 insertions, 55 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8307c9ebd309..96bc668c74b3 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1170,19 +1170,6 @@ static struct clk func_96m_fclk = {
1170 .set_rate = &omap2_clksel_set_rate, 1170 .set_rate = &omap2_clksel_set_rate,
1171}; 1171};
1172 1172
1173static const struct clksel hsmmc6_fclk_sel[] = {
1174 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1175 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1176 { .parent = NULL },
1177};
1178
1179static struct clk hsmmc6_fclk = {
1180 .name = "hsmmc6_fclk",
1181 .parent = &func_64m_fclk,
1182 .ops = &clkops_null,
1183 .recalc = &followparent_recalc,
1184};
1185
1186static const struct clksel_rate div2_1to8_rates[] = { 1173static const struct clksel_rate div2_1to8_rates[] = {
1187 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 1174 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1188 { .div = 8, .val = 1, .flags = RATE_IN_4430 }, 1175 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
@@ -1265,6 +1252,21 @@ static struct clk l4_wkup_clk_mux_ck = {
1265 .recalc = &omap2_clksel_recalc, 1252 .recalc = &omap2_clksel_recalc,
1266}; 1253};
1267 1254
1255static struct clk ocp_abe_iclk = {
1256 .name = "ocp_abe_iclk",
1257 .parent = &aess_fclk,
1258 .ops = &clkops_null,
1259 .recalc = &followparent_recalc,
1260};
1261
1262static struct clk per_abe_24m_fclk = {
1263 .name = "per_abe_24m_fclk",
1264 .parent = &dpll_abe_m2_ck,
1265 .ops = &clkops_null,
1266 .fixed_div = 4,
1267 .recalc = &omap_fixed_divisor_recalc,
1268};
1269
1268static const struct clksel per_abe_nc_fclk_div[] = { 1270static const struct clksel per_abe_nc_fclk_div[] = {
1269 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, 1271 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1270 { .parent = NULL }, 1272 { .parent = NULL },
@@ -1282,41 +1284,6 @@ static struct clk per_abe_nc_fclk = {
1282 .set_rate = &omap2_clksel_set_rate, 1284 .set_rate = &omap2_clksel_set_rate,
1283}; 1285};
1284 1286
1285static const struct clksel mcasp2_fclk_sel[] = {
1286 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1287 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1288 { .parent = NULL },
1289};
1290
1291static struct clk mcasp2_fclk = {
1292 .name = "mcasp2_fclk",
1293 .parent = &func_96m_fclk,
1294 .ops = &clkops_null,
1295 .recalc = &followparent_recalc,
1296};
1297
1298static struct clk mcasp3_fclk = {
1299 .name = "mcasp3_fclk",
1300 .parent = &func_96m_fclk,
1301 .ops = &clkops_null,
1302 .recalc = &followparent_recalc,
1303};
1304
1305static struct clk ocp_abe_iclk = {
1306 .name = "ocp_abe_iclk",
1307 .parent = &aess_fclk,
1308 .ops = &clkops_null,
1309 .recalc = &followparent_recalc,
1310};
1311
1312static struct clk per_abe_24m_fclk = {
1313 .name = "per_abe_24m_fclk",
1314 .parent = &dpll_abe_m2_ck,
1315 .ops = &clkops_null,
1316 .fixed_div = 4,
1317 .recalc = &omap_fixed_divisor_recalc,
1318};
1319
1320static const struct clksel pmd_stm_clock_mux_sel[] = { 1287static const struct clksel pmd_stm_clock_mux_sel[] = {
1321 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1288 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1322 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, 1289 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
@@ -1996,10 +1963,16 @@ static struct clk mcbsp3_fck = {
1996 .clkdm_name = "abe_clkdm", 1963 .clkdm_name = "abe_clkdm",
1997}; 1964};
1998 1965
1966static const struct clksel mcbsp4_sync_mux_sel[] = {
1967 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1968 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1969 { .parent = NULL },
1970};
1971
1999static struct clk mcbsp4_sync_mux_ck = { 1972static struct clk mcbsp4_sync_mux_ck = {
2000 .name = "mcbsp4_sync_mux_ck", 1973 .name = "mcbsp4_sync_mux_ck",
2001 .parent = &func_96m_fclk, 1974 .parent = &func_96m_fclk,
2002 .clksel = mcasp2_fclk_sel, 1975 .clksel = mcbsp4_sync_mux_sel,
2003 .init = &omap2_init_clksel_parent, 1976 .init = &omap2_init_clksel_parent,
2004 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 1977 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2005 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1978 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
@@ -2078,11 +2051,17 @@ static struct clk mcspi4_fck = {
2078 .recalc = &followparent_recalc, 2051 .recalc = &followparent_recalc,
2079}; 2052};
2080 2053
2054static const struct clksel hsmmc1_fclk_sel[] = {
2055 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2056 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2057 { .parent = NULL },
2058};
2059
2081/* Merged hsmmc1_fclk into mmc1 */ 2060/* Merged hsmmc1_fclk into mmc1 */
2082static struct clk mmc1_fck = { 2061static struct clk mmc1_fck = {
2083 .name = "mmc1_fck", 2062 .name = "mmc1_fck",
2084 .parent = &func_64m_fclk, 2063 .parent = &func_64m_fclk,
2085 .clksel = hsmmc6_fclk_sel, 2064 .clksel = hsmmc1_fclk_sel,
2086 .init = &omap2_init_clksel_parent, 2065 .init = &omap2_init_clksel_parent,
2087 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 2066 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2088 .clksel_mask = OMAP4430_CLKSEL_MASK, 2067 .clksel_mask = OMAP4430_CLKSEL_MASK,
@@ -2097,7 +2076,7 @@ static struct clk mmc1_fck = {
2097static struct clk mmc2_fck = { 2076static struct clk mmc2_fck = {
2098 .name = "mmc2_fck", 2077 .name = "mmc2_fck",
2099 .parent = &func_64m_fclk, 2078 .parent = &func_64m_fclk,
2100 .clksel = hsmmc6_fclk_sel, 2079 .clksel = hsmmc1_fclk_sel,
2101 .init = &omap2_init_clksel_parent, 2080 .init = &omap2_init_clksel_parent,
2102 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 2081 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2103 .clksel_mask = OMAP4430_CLKSEL_MASK, 2082 .clksel_mask = OMAP4430_CLKSEL_MASK,
@@ -3094,17 +3073,14 @@ static struct omap_clk omap44xx_clks[] = {
3094 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), 3073 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
3095 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), 3074 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
3096 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), 3075 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
3097 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
3098 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), 3076 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
3099 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), 3077 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
3100 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), 3078 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3101 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), 3079 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3102 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), 3080 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3103 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3104 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
3105 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
3106 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), 3081 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3107 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), 3082 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3083 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3108 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 3084 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
3109 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 3085 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
3110 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 3086 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),