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authorBenoit Cousson <b-cousson@ti.com>2010-09-27 16:02:55 -0400
committerPaul Walmsley <paul@pwsan.com>2010-09-27 16:02:55 -0400
commit1c03f42f01d212a79f7cd6e91eb8d8c624a843ec (patch)
tree5abfc8af10b350d5925937438be71fedea14b0ab /arch/arm/mach-omap2/clock44xx_data.c
parent0e43327191986e88efdc8717084aeb22db2cc8a9 (diff)
OMAP4: clock: Add optional clock nodes
OMAP4 IP optional clocks require explicit enable in module CTRLCLK register. In order to allow that we have to create artificial clock nodes that represent this clock inputs in the IP. Notes: - Temporary use OMAP3 names for GPIO optional clocks until the GPIO hwmod convertion is done. It will enforce the usage of OMAP4 names as the reference. - Temporary use OMAP3 names for TIMER main clock (gptX_fck) until TIMER hwmod convertion is done. During that convertion, the new name will have to be used. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c477
1 files changed, 417 insertions, 60 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8296ae04f77e..b94f21aa2581 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1288,6 +1288,16 @@ static struct clk aess_fck = {
1288 .recalc = &followparent_recalc, 1288 .recalc = &followparent_recalc,
1289}; 1289};
1290 1290
1291static struct clk bandgap_fclk = {
1292 .name = "bandgap_fclk",
1293 .ops = &clkops_omap2_dflt,
1294 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1295 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1296 .clkdm_name = "l4_wkup_clkdm",
1297 .parent = &sys_32k_ck,
1298 .recalc = &followparent_recalc,
1299};
1300
1291static struct clk des3des_fck = { 1301static struct clk des3des_fck = {
1292 .name = "des3des_fck", 1302 .name = "des3des_fck",
1293 .ops = &clkops_omap2_dflt, 1303 .ops = &clkops_omap2_dflt,
@@ -1348,6 +1358,46 @@ static struct clk dsp_fck = {
1348 .recalc = &followparent_recalc, 1358 .recalc = &followparent_recalc,
1349}; 1359};
1350 1360
1361static struct clk dss_sys_clk = {
1362 .name = "dss_sys_clk",
1363 .ops = &clkops_omap2_dflt,
1364 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1365 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1366 .clkdm_name = "l3_dss_clkdm",
1367 .parent = &syc_clk_div_ck,
1368 .recalc = &followparent_recalc,
1369};
1370
1371static struct clk dss_tv_clk = {
1372 .name = "dss_tv_clk",
1373 .ops = &clkops_omap2_dflt,
1374 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1375 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1376 .clkdm_name = "l3_dss_clkdm",
1377 .parent = &extalt_clkin_ck,
1378 .recalc = &followparent_recalc,
1379};
1380
1381static struct clk dss_dss_clk = {
1382 .name = "dss_dss_clk",
1383 .ops = &clkops_omap2_dflt,
1384 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1385 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1386 .clkdm_name = "l3_dss_clkdm",
1387 .parent = &dpll_per_m5_ck,
1388 .recalc = &followparent_recalc,
1389};
1390
1391static struct clk dss_48mhz_clk = {
1392 .name = "dss_48mhz_clk",
1393 .ops = &clkops_omap2_dflt,
1394 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1395 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1396 .clkdm_name = "l3_dss_clkdm",
1397 .parent = &func_48mc_fclk,
1398 .recalc = &followparent_recalc,
1399};
1400
1351static struct clk dss_fck = { 1401static struct clk dss_fck = {
1352 .name = "dss_fck", 1402 .name = "dss_fck",
1353 .ops = &clkops_omap2_dflt, 1403 .ops = &clkops_omap2_dflt,
@@ -1421,6 +1471,16 @@ static struct clk fpka_fck = {
1421 .recalc = &followparent_recalc, 1471 .recalc = &followparent_recalc,
1422}; 1472};
1423 1473
1474static struct clk gpio1_dbclk = {
1475 .name = "gpio1_dbclk",
1476 .ops = &clkops_omap2_dflt,
1477 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1478 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1479 .clkdm_name = "l4_wkup_clkdm",
1480 .parent = &sys_32k_ck,
1481 .recalc = &followparent_recalc,
1482};
1483
1424static struct clk gpio1_ick = { 1484static struct clk gpio1_ick = {
1425 .name = "gpio1_ick", 1485 .name = "gpio1_ick",
1426 .ops = &clkops_omap2_dflt, 1486 .ops = &clkops_omap2_dflt,
@@ -1431,6 +1491,16 @@ static struct clk gpio1_ick = {
1431 .recalc = &followparent_recalc, 1491 .recalc = &followparent_recalc,
1432}; 1492};
1433 1493
1494static struct clk gpio2_dbclk = {
1495 .name = "gpio2_dbclk",
1496 .ops = &clkops_omap2_dflt,
1497 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1498 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1499 .clkdm_name = "l4_per_clkdm",
1500 .parent = &sys_32k_ck,
1501 .recalc = &followparent_recalc,
1502};
1503
1434static struct clk gpio2_ick = { 1504static struct clk gpio2_ick = {
1435 .name = "gpio2_ick", 1505 .name = "gpio2_ick",
1436 .ops = &clkops_omap2_dflt, 1506 .ops = &clkops_omap2_dflt,
@@ -1441,6 +1511,16 @@ static struct clk gpio2_ick = {
1441 .recalc = &followparent_recalc, 1511 .recalc = &followparent_recalc,
1442}; 1512};
1443 1513
1514static struct clk gpio3_dbclk = {
1515 .name = "gpio3_dbclk",
1516 .ops = &clkops_omap2_dflt,
1517 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1518 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1519 .clkdm_name = "l4_per_clkdm",
1520 .parent = &sys_32k_ck,
1521 .recalc = &followparent_recalc,
1522};
1523
1444static struct clk gpio3_ick = { 1524static struct clk gpio3_ick = {
1445 .name = "gpio3_ick", 1525 .name = "gpio3_ick",
1446 .ops = &clkops_omap2_dflt, 1526 .ops = &clkops_omap2_dflt,
@@ -1451,6 +1531,16 @@ static struct clk gpio3_ick = {
1451 .recalc = &followparent_recalc, 1531 .recalc = &followparent_recalc,
1452}; 1532};
1453 1533
1534static struct clk gpio4_dbclk = {
1535 .name = "gpio4_dbclk",
1536 .ops = &clkops_omap2_dflt,
1537 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1538 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1539 .clkdm_name = "l4_per_clkdm",
1540 .parent = &sys_32k_ck,
1541 .recalc = &followparent_recalc,
1542};
1543
1454static struct clk gpio4_ick = { 1544static struct clk gpio4_ick = {
1455 .name = "gpio4_ick", 1545 .name = "gpio4_ick",
1456 .ops = &clkops_omap2_dflt, 1546 .ops = &clkops_omap2_dflt,
@@ -1461,6 +1551,16 @@ static struct clk gpio4_ick = {
1461 .recalc = &followparent_recalc, 1551 .recalc = &followparent_recalc,
1462}; 1552};
1463 1553
1554static struct clk gpio5_dbclk = {
1555 .name = "gpio5_dbclk",
1556 .ops = &clkops_omap2_dflt,
1557 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1558 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1559 .clkdm_name = "l4_per_clkdm",
1560 .parent = &sys_32k_ck,
1561 .recalc = &followparent_recalc,
1562};
1563
1464static struct clk gpio5_ick = { 1564static struct clk gpio5_ick = {
1465 .name = "gpio5_ick", 1565 .name = "gpio5_ick",
1466 .ops = &clkops_omap2_dflt, 1566 .ops = &clkops_omap2_dflt,
@@ -1471,6 +1571,16 @@ static struct clk gpio5_ick = {
1471 .recalc = &followparent_recalc, 1571 .recalc = &followparent_recalc,
1472}; 1572};
1473 1573
1574static struct clk gpio6_dbclk = {
1575 .name = "gpio6_dbclk",
1576 .ops = &clkops_omap2_dflt,
1577 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1578 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1579 .clkdm_name = "l4_per_clkdm",
1580 .parent = &sys_32k_ck,
1581 .recalc = &followparent_recalc,
1582};
1583
1474static struct clk gpio6_ick = { 1584static struct clk gpio6_ick = {
1475 .name = "gpio6_ick", 1585 .name = "gpio6_ick",
1476 .ops = &clkops_omap2_dflt, 1586 .ops = &clkops_omap2_dflt,
@@ -1593,6 +1703,16 @@ static struct clk ipu_fck = {
1593 .recalc = &followparent_recalc, 1703 .recalc = &followparent_recalc,
1594}; 1704};
1595 1705
1706static struct clk iss_ctrlclk = {
1707 .name = "iss_ctrlclk",
1708 .ops = &clkops_omap2_dflt,
1709 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1710 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1711 .clkdm_name = "iss_clkdm",
1712 .parent = &func_96m_fclk,
1713 .recalc = &followparent_recalc,
1714};
1715
1596static struct clk iss_fck = { 1716static struct clk iss_fck = {
1597 .name = "iss_fck", 1717 .name = "iss_fck",
1598 .ops = &clkops_omap2_dflt, 1718 .ops = &clkops_omap2_dflt,
@@ -1917,6 +2037,26 @@ static struct clk mmc5_fck = {
1917 .recalc = &followparent_recalc, 2037 .recalc = &followparent_recalc,
1918}; 2038};
1919 2039
2040static struct clk ocp2scp_usb_phy_clk32k = {
2041 .name = "ocp2scp_usb_phy_clk32k",
2042 .ops = &clkops_omap2_dflt,
2043 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2044 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2045 .clkdm_name = "l3_init_clkdm",
2046 .parent = &sys_32k_ck,
2047 .recalc = &followparent_recalc,
2048};
2049
2050static struct clk ocp2scp_usb_phy_phy_48m = {
2051 .name = "ocp2scp_usb_phy_phy_48m",
2052 .ops = &clkops_omap2_dflt,
2053 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2054 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2055 .clkdm_name = "l3_init_clkdm",
2056 .parent = &func_48m_fclk,
2057 .recalc = &followparent_recalc,
2058};
2059
1920static struct clk ocp_wp_noc_ick = { 2060static struct clk ocp_wp_noc_ick = {
1921 .name = "ocp_wp_noc_ick", 2061 .name = "ocp_wp_noc_ick",
1922 .ops = &clkops_omap2_dflt, 2062 .ops = &clkops_omap2_dflt,
@@ -1957,6 +2097,46 @@ static struct clk sl2if_ick = {
1957 .recalc = &followparent_recalc, 2097 .recalc = &followparent_recalc,
1958}; 2098};
1959 2099
2100static struct clk slimbus1_fclk_1 = {
2101 .name = "slimbus1_fclk_1",
2102 .ops = &clkops_omap2_dflt,
2103 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2104 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2105 .clkdm_name = "abe_clkdm",
2106 .parent = &func_24m_clk,
2107 .recalc = &followparent_recalc,
2108};
2109
2110static struct clk slimbus1_fclk_0 = {
2111 .name = "slimbus1_fclk_0",
2112 .ops = &clkops_omap2_dflt,
2113 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2114 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2115 .clkdm_name = "abe_clkdm",
2116 .parent = &abe_24m_fclk,
2117 .recalc = &followparent_recalc,
2118};
2119
2120static struct clk slimbus1_fclk_2 = {
2121 .name = "slimbus1_fclk_2",
2122 .ops = &clkops_omap2_dflt,
2123 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2124 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2125 .clkdm_name = "abe_clkdm",
2126 .parent = &pad_clks_ck,
2127 .recalc = &followparent_recalc,
2128};
2129
2130static struct clk slimbus1_slimbus_clk = {
2131 .name = "slimbus1_slimbus_clk",
2132 .ops = &clkops_omap2_dflt,
2133 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2134 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2135 .clkdm_name = "abe_clkdm",
2136 .parent = &slimbus_clk,
2137 .recalc = &followparent_recalc,
2138};
2139
1960static struct clk slimbus1_fck = { 2140static struct clk slimbus1_fck = {
1961 .name = "slimbus1_fck", 2141 .name = "slimbus1_fck",
1962 .ops = &clkops_omap2_dflt, 2142 .ops = &clkops_omap2_dflt,
@@ -1967,6 +2147,36 @@ static struct clk slimbus1_fck = {
1967 .recalc = &followparent_recalc, 2147 .recalc = &followparent_recalc,
1968}; 2148};
1969 2149
2150static struct clk slimbus2_fclk_1 = {
2151 .name = "slimbus2_fclk_1",
2152 .ops = &clkops_omap2_dflt,
2153 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2154 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2155 .clkdm_name = "l4_per_clkdm",
2156 .parent = &per_abe_24m_fclk,
2157 .recalc = &followparent_recalc,
2158};
2159
2160static struct clk slimbus2_fclk_0 = {
2161 .name = "slimbus2_fclk_0",
2162 .ops = &clkops_omap2_dflt,
2163 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2164 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2165 .clkdm_name = "l4_per_clkdm",
2166 .parent = &func_24mc_fclk,
2167 .recalc = &followparent_recalc,
2168};
2169
2170static struct clk slimbus2_slimbus_clk = {
2171 .name = "slimbus2_slimbus_clk",
2172 .ops = &clkops_omap2_dflt,
2173 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2174 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2175 .clkdm_name = "l4_per_clkdm",
2176 .parent = &pad_slimbus_core_clks_ck,
2177 .recalc = &followparent_recalc,
2178};
2179
1970static struct clk slimbus2_fck = { 2180static struct clk slimbus2_fck = {
1971 .name = "slimbus2_fck", 2181 .name = "slimbus2_fck",
1972 .ops = &clkops_omap2_dflt, 2182 .ops = &clkops_omap2_dflt,
@@ -2228,6 +2438,120 @@ static struct clk usb_host_fs_fck = {
2228 .recalc = &followparent_recalc, 2438 .recalc = &followparent_recalc,
2229}; 2439};
2230 2440
2441static struct clk usb_host_hs_utmi_p3_clk = {
2442 .name = "usb_host_hs_utmi_p3_clk",
2443 .ops = &clkops_omap2_dflt,
2444 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2445 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2446 .clkdm_name = "l3_init_clkdm",
2447 .parent = &init_60m_fclk,
2448 .recalc = &followparent_recalc,
2449};
2450
2451static struct clk usb_host_hs_hsic60m_p1_clk = {
2452 .name = "usb_host_hs_hsic60m_p1_clk",
2453 .ops = &clkops_omap2_dflt,
2454 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2455 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2456 .clkdm_name = "l3_init_clkdm",
2457 .parent = &init_60m_fclk,
2458 .recalc = &followparent_recalc,
2459};
2460
2461static struct clk usb_host_hs_hsic60m_p2_clk = {
2462 .name = "usb_host_hs_hsic60m_p2_clk",
2463 .ops = &clkops_omap2_dflt,
2464 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2465 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2466 .clkdm_name = "l3_init_clkdm",
2467 .parent = &init_60m_fclk,
2468 .recalc = &followparent_recalc,
2469};
2470
2471static const struct clksel utmi_p1_gfclk_sel[] = {
2472 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2473 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2474 { .parent = NULL },
2475};
2476
2477static struct clk utmi_p1_gfclk = {
2478 .name = "utmi_p1_gfclk",
2479 .parent = &init_60m_fclk,
2480 .clksel = utmi_p1_gfclk_sel,
2481 .init = &omap2_init_clksel_parent,
2482 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2483 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2484 .ops = &clkops_null,
2485 .recalc = &omap2_clksel_recalc,
2486};
2487
2488static struct clk usb_host_hs_utmi_p1_clk = {
2489 .name = "usb_host_hs_utmi_p1_clk",
2490 .ops = &clkops_omap2_dflt,
2491 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2492 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2493 .clkdm_name = "l3_init_clkdm",
2494 .parent = &utmi_p1_gfclk,
2495 .recalc = &followparent_recalc,
2496};
2497
2498static const struct clksel utmi_p2_gfclk_sel[] = {
2499 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2500 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2501 { .parent = NULL },
2502};
2503
2504static struct clk utmi_p2_gfclk = {
2505 .name = "utmi_p2_gfclk",
2506 .parent = &init_60m_fclk,
2507 .clksel = utmi_p2_gfclk_sel,
2508 .init = &omap2_init_clksel_parent,
2509 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2510 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2511 .ops = &clkops_null,
2512 .recalc = &omap2_clksel_recalc,
2513};
2514
2515static struct clk usb_host_hs_utmi_p2_clk = {
2516 .name = "usb_host_hs_utmi_p2_clk",
2517 .ops = &clkops_omap2_dflt,
2518 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2519 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2520 .clkdm_name = "l3_init_clkdm",
2521 .parent = &utmi_p2_gfclk,
2522 .recalc = &followparent_recalc,
2523};
2524
2525static struct clk usb_host_hs_hsic480m_p1_clk = {
2526 .name = "usb_host_hs_hsic480m_p1_clk",
2527 .ops = &clkops_omap2_dflt,
2528 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2529 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2530 .clkdm_name = "l3_init_clkdm",
2531 .parent = &dpll_usb_m2_ck,
2532 .recalc = &followparent_recalc,
2533};
2534
2535static struct clk usb_host_hs_hsic480m_p2_clk = {
2536 .name = "usb_host_hs_hsic480m_p2_clk",
2537 .ops = &clkops_omap2_dflt,
2538 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2539 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2540 .clkdm_name = "l3_init_clkdm",
2541 .parent = &dpll_usb_m2_ck,
2542 .recalc = &followparent_recalc,
2543};
2544
2545static struct clk usb_host_hs_func48mclk = {
2546 .name = "usb_host_hs_func48mclk",
2547 .ops = &clkops_omap2_dflt,
2548 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2549 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2550 .clkdm_name = "l3_init_clkdm",
2551 .parent = &func_48mc_fclk,
2552 .recalc = &followparent_recalc,
2553};
2554
2231static struct clk usb_host_hs_fck = { 2555static struct clk usb_host_hs_fck = {
2232 .name = "usb_host_hs_fck", 2556 .name = "usb_host_hs_fck",
2233 .ops = &clkops_omap2_dflt, 2557 .ops = &clkops_omap2_dflt,
@@ -2238,6 +2562,33 @@ static struct clk usb_host_hs_fck = {
2238 .recalc = &followparent_recalc, 2562 .recalc = &followparent_recalc,
2239}; 2563};
2240 2564
2565static const struct clksel otg_60m_gfclk_sel[] = {
2566 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2567 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2568 { .parent = NULL },
2569};
2570
2571static struct clk otg_60m_gfclk = {
2572 .name = "otg_60m_gfclk",
2573 .parent = &utmi_phy_clkout_ck,
2574 .clksel = otg_60m_gfclk_sel,
2575 .init = &omap2_init_clksel_parent,
2576 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2577 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2578 .ops = &clkops_null,
2579 .recalc = &omap2_clksel_recalc,
2580};
2581
2582static struct clk usb_otg_hs_xclk = {
2583 .name = "usb_otg_hs_xclk",
2584 .ops = &clkops_omap2_dflt,
2585 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2586 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2587 .clkdm_name = "l3_init_clkdm",
2588 .parent = &otg_60m_gfclk,
2589 .recalc = &followparent_recalc,
2590};
2591
2241static struct clk usb_otg_hs_ick = { 2592static struct clk usb_otg_hs_ick = {
2242 .name = "usb_otg_hs_ick", 2593 .name = "usb_otg_hs_ick",
2243 .ops = &clkops_omap2_dflt, 2594 .ops = &clkops_omap2_dflt,
@@ -2248,6 +2599,36 @@ static struct clk usb_otg_hs_ick = {
2248 .recalc = &followparent_recalc, 2599 .recalc = &followparent_recalc,
2249}; 2600};
2250 2601
2602static struct clk usb_tll_hs_usb_ch2_clk = {
2603 .name = "usb_tll_hs_usb_ch2_clk",
2604 .ops = &clkops_omap2_dflt,
2605 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2606 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2607 .clkdm_name = "l3_init_clkdm",
2608 .parent = &init_60m_fclk,
2609 .recalc = &followparent_recalc,
2610};
2611
2612static struct clk usb_tll_hs_usb_ch0_clk = {
2613 .name = "usb_tll_hs_usb_ch0_clk",
2614 .ops = &clkops_omap2_dflt,
2615 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2616 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2617 .clkdm_name = "l3_init_clkdm",
2618 .parent = &init_60m_fclk,
2619 .recalc = &followparent_recalc,
2620};
2621
2622static struct clk usb_tll_hs_usb_ch1_clk = {
2623 .name = "usb_tll_hs_usb_ch1_clk",
2624 .ops = &clkops_omap2_dflt,
2625 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2626 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2627 .clkdm_name = "l3_init_clkdm",
2628 .parent = &init_60m_fclk,
2629 .recalc = &followparent_recalc,
2630};
2631
2251static struct clk usb_tll_hs_ick = { 2632static struct clk usb_tll_hs_ick = {
2252 .name = "usb_tll_hs_ick", 2633 .name = "usb_tll_hs_ick",
2253 .ops = &clkops_omap2_dflt, 2634 .ops = &clkops_omap2_dflt,
@@ -2289,23 +2670,6 @@ static struct clk wd_timer3_fck = {
2289}; 2670};
2290 2671
2291/* Remaining optional clocks */ 2672/* Remaining optional clocks */
2292static const struct clksel otg_60m_gfclk_sel[] = {
2293 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2294 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2295 { .parent = NULL },
2296};
2297
2298static struct clk otg_60m_gfclk_ck = {
2299 .name = "otg_60m_gfclk_ck",
2300 .parent = &utmi_phy_clkout_ck,
2301 .clksel = otg_60m_gfclk_sel,
2302 .init = &omap2_init_clksel_parent,
2303 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2304 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2305 .ops = &clkops_null,
2306 .recalc = &omap2_clksel_recalc,
2307};
2308
2309static const struct clksel stm_clk_div_div[] = { 2673static const struct clksel stm_clk_div_div[] = {
2310 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, 2674 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2311 { .parent = NULL }, 2675 { .parent = NULL },
@@ -2363,40 +2727,6 @@ static struct clk usim_fclk = {
2363 .set_rate = &omap2_clksel_set_rate, 2727 .set_rate = &omap2_clksel_set_rate,
2364}; 2728};
2365 2729
2366static const struct clksel utmi_p1_gfclk_sel[] = {
2367 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2368 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2369 { .parent = NULL },
2370};
2371
2372static struct clk utmi_p1_gfclk_ck = {
2373 .name = "utmi_p1_gfclk_ck",
2374 .parent = &init_60m_fclk,
2375 .clksel = utmi_p1_gfclk_sel,
2376 .init = &omap2_init_clksel_parent,
2377 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2378 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2379 .ops = &clkops_null,
2380 .recalc = &omap2_clksel_recalc,
2381};
2382
2383static const struct clksel utmi_p2_gfclk_sel[] = {
2384 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2385 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2386 { .parent = NULL },
2387};
2388
2389static struct clk utmi_p2_gfclk_ck = {
2390 .name = "utmi_p2_gfclk_ck",
2391 .parent = &init_60m_fclk,
2392 .clksel = utmi_p2_gfclk_sel,
2393 .init = &omap2_init_clksel_parent,
2394 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2395 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2396 .ops = &clkops_null,
2397 .recalc = &omap2_clksel_recalc,
2398};
2399
2400/* 2730/*
2401 * clkdev 2731 * clkdev
2402 */ 2732 */
@@ -2491,21 +2821,32 @@ static struct omap_clk omap44xx_clks[] = {
2491 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 2821 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2492 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 2822 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2493 CLK(NULL, "aess_fck", &aess_fck, CK_443X), 2823 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
2824 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
2494 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), 2825 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
2495 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 2826 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2496 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 2827 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
2497 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), 2828 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
2829 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
2830 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
2831 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
2832 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
2498 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 2833 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
2499 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), 2834 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
2500 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), 2835 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
2501 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), 2836 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
2502 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 2837 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2503 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), 2838 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
2839 CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X),
2504 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), 2840 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
2841 CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X),
2505 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), 2842 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
2843 CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X),
2506 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), 2844 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
2845 CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X),
2507 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), 2846 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
2847 CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X),
2508 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), 2848 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
2849 CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X),
2509 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 2850 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2510 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 2851 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2511 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), 2852 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
@@ -2516,6 +2857,7 @@ static struct omap_clk omap44xx_clks[] = {
2516 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), 2857 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
2517 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), 2858 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
2518 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), 2859 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
2860 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
2519 CLK(NULL, "iss_fck", &iss_fck, CK_443X), 2861 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
2520 CLK(NULL, "iva_fck", &iva_fck, CK_443X), 2862 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
2521 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), 2863 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
@@ -2541,11 +2883,20 @@ static struct omap_clk omap44xx_clks[] = {
2541 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), 2883 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
2542 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), 2884 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
2543 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), 2885 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
2886 CLK(NULL, "ocp2scp_usb_phy_clk32k", &ocp2scp_usb_phy_clk32k, CK_443X),
2887 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
2544 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), 2888 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
2545 CLK("omap_rng", "ick", &rng_ick, CK_443X), 2889 CLK("omap_rng", "ick", &rng_ick, CK_443X),
2546 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 2890 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
2547 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), 2891 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
2892 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
2893 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
2894 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
2895 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
2548 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), 2896 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
2897 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
2898 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
2899 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
2549 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), 2900 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
2550 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), 2901 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
2551 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), 2902 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
@@ -2566,24 +2917,30 @@ static struct omap_clk omap44xx_clks[] = {
2566 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 2917 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2567 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 2918 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2568 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 2919 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2920 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
2921 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
2922 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
2923 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
2924 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
2925 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
2926 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
2927 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
2928 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
2929 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
2569 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), 2930 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
2931 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
2932 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
2570 CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), 2933 CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X),
2934 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
2935 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
2936 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
2571 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), 2937 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
2572 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 2938 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2573 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), 2939 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
2574 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), 2940 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
2575 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2576 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 2941 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2577 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 2942 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
2578 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 2943 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2579 CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
2580 CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
2581 CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
2582 CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
2583 CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
2584 CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
2585 CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
2586 CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
2587 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 2944 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
2588 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 2945 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
2589 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), 2946 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 15:40:00 -0400