diff options
author | Paul Walmsley <paul@pwsan.com> | 2011-02-25 17:39:30 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2011-03-07 22:04:03 -0500 |
commit | ec538e30f7eded2c4af8d9184619a3de65bc378e (patch) | |
tree | 5a5f7589c31e9c965e250f67b8b2339d9ae5bfe6 /arch/arm/mach-omap2/clock3xxx_data.c | |
parent | a1d5562315a1e911c8448b7fac33c966f9cb6294 (diff) |
OMAP3: clock: use autoidle clkops for all autoidle-controllable interface clocks
Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/clock3xxx_data.c | 149 |
1 files changed, 77 insertions, 72 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 65b79e6afb53..305b5f75c44f 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
@@ -2,7 +2,7 @@ | |||
2 | * OMAP3 clock data | 2 | * OMAP3 clock data |
3 | * | 3 | * |
4 | * Copyright (C) 2007-2010 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2007-2010 Nokia Corporation | 5 | * Copyright (C) 2007-2011 Nokia Corporation |
6 | * | 6 | * |
7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
8 | * With many device clock fixes by Kevin Hilman and Jouni Högander | 8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
@@ -1205,7 +1205,10 @@ static const struct clksel gfx_l3_clksel[] = { | |||
1205 | { .parent = NULL } | 1205 | { .parent = NULL } |
1206 | }; | 1206 | }; |
1207 | 1207 | ||
1208 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ | 1208 | /* |
1209 | * Virtual parent clock for gfx_l3_ick and gfx_l3_fck | ||
1210 | * This interface clock does not have a CM_AUTOIDLE bit | ||
1211 | */ | ||
1209 | static struct clk gfx_l3_ck = { | 1212 | static struct clk gfx_l3_ck = { |
1210 | .name = "gfx_l3_ck", | 1213 | .name = "gfx_l3_ck", |
1211 | .ops = &clkops_omap2_dflt_wait, | 1214 | .ops = &clkops_omap2_dflt_wait, |
@@ -1304,6 +1307,7 @@ static struct clk sgx_fck = { | |||
1304 | .round_rate = &omap2_clksel_round_rate | 1307 | .round_rate = &omap2_clksel_round_rate |
1305 | }; | 1308 | }; |
1306 | 1309 | ||
1310 | /* This interface clock does not have a CM_AUTOIDLE bit */ | ||
1307 | static struct clk sgx_ick = { | 1311 | static struct clk sgx_ick = { |
1308 | .name = "sgx_ick", | 1312 | .name = "sgx_ick", |
1309 | .ops = &clkops_omap2_dflt_wait, | 1313 | .ops = &clkops_omap2_dflt_wait, |
@@ -1328,7 +1332,7 @@ static struct clk d2d_26m_fck = { | |||
1328 | 1332 | ||
1329 | static struct clk modem_fck = { | 1333 | static struct clk modem_fck = { |
1330 | .name = "modem_fck", | 1334 | .name = "modem_fck", |
1331 | .ops = &clkops_omap2_dflt_wait, | 1335 | .ops = &clkops_omap2_mdmclk_dflt_wait, |
1332 | .parent = &sys_ck, | 1336 | .parent = &sys_ck, |
1333 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1337 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1334 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, | 1338 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, |
@@ -1338,7 +1342,7 @@ static struct clk modem_fck = { | |||
1338 | 1342 | ||
1339 | static struct clk sad2d_ick = { | 1343 | static struct clk sad2d_ick = { |
1340 | .name = "sad2d_ick", | 1344 | .name = "sad2d_ick", |
1341 | .ops = &clkops_omap2_dflt_wait, | 1345 | .ops = &clkops_omap2_iclk_dflt_wait, |
1342 | .parent = &l3_ick, | 1346 | .parent = &l3_ick, |
1343 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1347 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1344 | .enable_bit = OMAP3430_EN_SAD2D_SHIFT, | 1348 | .enable_bit = OMAP3430_EN_SAD2D_SHIFT, |
@@ -1348,7 +1352,7 @@ static struct clk sad2d_ick = { | |||
1348 | 1352 | ||
1349 | static struct clk mad2d_ick = { | 1353 | static struct clk mad2d_ick = { |
1350 | .name = "mad2d_ick", | 1354 | .name = "mad2d_ick", |
1351 | .ops = &clkops_omap2_dflt_wait, | 1355 | .ops = &clkops_omap2_iclk_dflt_wait, |
1352 | .parent = &l3_ick, | 1356 | .parent = &l3_ick, |
1353 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | 1357 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
1354 | .enable_bit = OMAP3430_EN_MAD2D_SHIFT, | 1358 | .enable_bit = OMAP3430_EN_MAD2D_SHIFT, |
@@ -1718,7 +1722,7 @@ static struct clk core_l3_ick = { | |||
1718 | 1722 | ||
1719 | static struct clk hsotgusb_ick_3430es1 = { | 1723 | static struct clk hsotgusb_ick_3430es1 = { |
1720 | .name = "hsotgusb_ick", | 1724 | .name = "hsotgusb_ick", |
1721 | .ops = &clkops_omap2_dflt, | 1725 | .ops = &clkops_omap2_iclk_dflt, |
1722 | .parent = &core_l3_ick, | 1726 | .parent = &core_l3_ick, |
1723 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1727 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1724 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | 1728 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
@@ -1728,7 +1732,7 @@ static struct clk hsotgusb_ick_3430es1 = { | |||
1728 | 1732 | ||
1729 | static struct clk hsotgusb_ick_3430es2 = { | 1733 | static struct clk hsotgusb_ick_3430es2 = { |
1730 | .name = "hsotgusb_ick", | 1734 | .name = "hsotgusb_ick", |
1731 | .ops = &clkops_omap3430es2_hsotgusb_wait, | 1735 | .ops = &clkops_omap3430es2_iclk_hsotgusb_wait, |
1732 | .parent = &core_l3_ick, | 1736 | .parent = &core_l3_ick, |
1733 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1737 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1734 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | 1738 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
@@ -1736,6 +1740,7 @@ static struct clk hsotgusb_ick_3430es2 = { | |||
1736 | .recalc = &followparent_recalc, | 1740 | .recalc = &followparent_recalc, |
1737 | }; | 1741 | }; |
1738 | 1742 | ||
1743 | /* This interface clock does not have a CM_AUTOIDLE bit */ | ||
1739 | static struct clk sdrc_ick = { | 1744 | static struct clk sdrc_ick = { |
1740 | .name = "sdrc_ick", | 1745 | .name = "sdrc_ick", |
1741 | .ops = &clkops_omap2_dflt_wait, | 1746 | .ops = &clkops_omap2_dflt_wait, |
@@ -1767,7 +1772,7 @@ static struct clk security_l3_ick = { | |||
1767 | 1772 | ||
1768 | static struct clk pka_ick = { | 1773 | static struct clk pka_ick = { |
1769 | .name = "pka_ick", | 1774 | .name = "pka_ick", |
1770 | .ops = &clkops_omap2_dflt_wait, | 1775 | .ops = &clkops_omap2_iclk_dflt_wait, |
1771 | .parent = &security_l3_ick, | 1776 | .parent = &security_l3_ick, |
1772 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1777 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1773 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | 1778 | .enable_bit = OMAP3430_EN_PKA_SHIFT, |
@@ -1786,7 +1791,7 @@ static struct clk core_l4_ick = { | |||
1786 | 1791 | ||
1787 | static struct clk usbtll_ick = { | 1792 | static struct clk usbtll_ick = { |
1788 | .name = "usbtll_ick", | 1793 | .name = "usbtll_ick", |
1789 | .ops = &clkops_omap2_dflt_wait, | 1794 | .ops = &clkops_omap2_iclk_dflt_wait, |
1790 | .parent = &core_l4_ick, | 1795 | .parent = &core_l4_ick, |
1791 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | 1796 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
1792 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1797 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
@@ -1796,7 +1801,7 @@ static struct clk usbtll_ick = { | |||
1796 | 1801 | ||
1797 | static struct clk mmchs3_ick = { | 1802 | static struct clk mmchs3_ick = { |
1798 | .name = "mmchs3_ick", | 1803 | .name = "mmchs3_ick", |
1799 | .ops = &clkops_omap2_dflt_wait, | 1804 | .ops = &clkops_omap2_iclk_dflt_wait, |
1800 | .parent = &core_l4_ick, | 1805 | .parent = &core_l4_ick, |
1801 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1806 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1802 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1807 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
@@ -1807,7 +1812,7 @@ static struct clk mmchs3_ick = { | |||
1807 | /* Intersystem Communication Registers - chassis mode only */ | 1812 | /* Intersystem Communication Registers - chassis mode only */ |
1808 | static struct clk icr_ick = { | 1813 | static struct clk icr_ick = { |
1809 | .name = "icr_ick", | 1814 | .name = "icr_ick", |
1810 | .ops = &clkops_omap2_dflt_wait, | 1815 | .ops = &clkops_omap2_iclk_dflt_wait, |
1811 | .parent = &core_l4_ick, | 1816 | .parent = &core_l4_ick, |
1812 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1817 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1813 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | 1818 | .enable_bit = OMAP3430_EN_ICR_SHIFT, |
@@ -1817,7 +1822,7 @@ static struct clk icr_ick = { | |||
1817 | 1822 | ||
1818 | static struct clk aes2_ick = { | 1823 | static struct clk aes2_ick = { |
1819 | .name = "aes2_ick", | 1824 | .name = "aes2_ick", |
1820 | .ops = &clkops_omap2_dflt_wait, | 1825 | .ops = &clkops_omap2_iclk_dflt_wait, |
1821 | .parent = &core_l4_ick, | 1826 | .parent = &core_l4_ick, |
1822 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1827 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1823 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | 1828 | .enable_bit = OMAP3430_EN_AES2_SHIFT, |
@@ -1827,7 +1832,7 @@ static struct clk aes2_ick = { | |||
1827 | 1832 | ||
1828 | static struct clk sha12_ick = { | 1833 | static struct clk sha12_ick = { |
1829 | .name = "sha12_ick", | 1834 | .name = "sha12_ick", |
1830 | .ops = &clkops_omap2_dflt_wait, | 1835 | .ops = &clkops_omap2_iclk_dflt_wait, |
1831 | .parent = &core_l4_ick, | 1836 | .parent = &core_l4_ick, |
1832 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1837 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1833 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | 1838 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, |
@@ -1837,7 +1842,7 @@ static struct clk sha12_ick = { | |||
1837 | 1842 | ||
1838 | static struct clk des2_ick = { | 1843 | static struct clk des2_ick = { |
1839 | .name = "des2_ick", | 1844 | .name = "des2_ick", |
1840 | .ops = &clkops_omap2_dflt_wait, | 1845 | .ops = &clkops_omap2_iclk_dflt_wait, |
1841 | .parent = &core_l4_ick, | 1846 | .parent = &core_l4_ick, |
1842 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1847 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1843 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | 1848 | .enable_bit = OMAP3430_EN_DES2_SHIFT, |
@@ -1847,7 +1852,7 @@ static struct clk des2_ick = { | |||
1847 | 1852 | ||
1848 | static struct clk mmchs2_ick = { | 1853 | static struct clk mmchs2_ick = { |
1849 | .name = "mmchs2_ick", | 1854 | .name = "mmchs2_ick", |
1850 | .ops = &clkops_omap2_dflt_wait, | 1855 | .ops = &clkops_omap2_iclk_dflt_wait, |
1851 | .parent = &core_l4_ick, | 1856 | .parent = &core_l4_ick, |
1852 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1857 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1853 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1858 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
@@ -1857,7 +1862,7 @@ static struct clk mmchs2_ick = { | |||
1857 | 1862 | ||
1858 | static struct clk mmchs1_ick = { | 1863 | static struct clk mmchs1_ick = { |
1859 | .name = "mmchs1_ick", | 1864 | .name = "mmchs1_ick", |
1860 | .ops = &clkops_omap2_dflt_wait, | 1865 | .ops = &clkops_omap2_iclk_dflt_wait, |
1861 | .parent = &core_l4_ick, | 1866 | .parent = &core_l4_ick, |
1862 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1867 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1863 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | 1868 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
@@ -1867,7 +1872,7 @@ static struct clk mmchs1_ick = { | |||
1867 | 1872 | ||
1868 | static struct clk mspro_ick = { | 1873 | static struct clk mspro_ick = { |
1869 | .name = "mspro_ick", | 1874 | .name = "mspro_ick", |
1870 | .ops = &clkops_omap2_dflt_wait, | 1875 | .ops = &clkops_omap2_iclk_dflt_wait, |
1871 | .parent = &core_l4_ick, | 1876 | .parent = &core_l4_ick, |
1872 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1877 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1873 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | 1878 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
@@ -1877,7 +1882,7 @@ static struct clk mspro_ick = { | |||
1877 | 1882 | ||
1878 | static struct clk hdq_ick = { | 1883 | static struct clk hdq_ick = { |
1879 | .name = "hdq_ick", | 1884 | .name = "hdq_ick", |
1880 | .ops = &clkops_omap2_dflt_wait, | 1885 | .ops = &clkops_omap2_iclk_dflt_wait, |
1881 | .parent = &core_l4_ick, | 1886 | .parent = &core_l4_ick, |
1882 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1887 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1883 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | 1888 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
@@ -1887,7 +1892,7 @@ static struct clk hdq_ick = { | |||
1887 | 1892 | ||
1888 | static struct clk mcspi4_ick = { | 1893 | static struct clk mcspi4_ick = { |
1889 | .name = "mcspi4_ick", | 1894 | .name = "mcspi4_ick", |
1890 | .ops = &clkops_omap2_dflt_wait, | 1895 | .ops = &clkops_omap2_iclk_dflt_wait, |
1891 | .parent = &core_l4_ick, | 1896 | .parent = &core_l4_ick, |
1892 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1897 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1893 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1898 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
@@ -1897,7 +1902,7 @@ static struct clk mcspi4_ick = { | |||
1897 | 1902 | ||
1898 | static struct clk mcspi3_ick = { | 1903 | static struct clk mcspi3_ick = { |
1899 | .name = "mcspi3_ick", | 1904 | .name = "mcspi3_ick", |
1900 | .ops = &clkops_omap2_dflt_wait, | 1905 | .ops = &clkops_omap2_iclk_dflt_wait, |
1901 | .parent = &core_l4_ick, | 1906 | .parent = &core_l4_ick, |
1902 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1907 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1903 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1908 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
@@ -1907,7 +1912,7 @@ static struct clk mcspi3_ick = { | |||
1907 | 1912 | ||
1908 | static struct clk mcspi2_ick = { | 1913 | static struct clk mcspi2_ick = { |
1909 | .name = "mcspi2_ick", | 1914 | .name = "mcspi2_ick", |
1910 | .ops = &clkops_omap2_dflt_wait, | 1915 | .ops = &clkops_omap2_iclk_dflt_wait, |
1911 | .parent = &core_l4_ick, | 1916 | .parent = &core_l4_ick, |
1912 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1917 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1913 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1918 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
@@ -1917,7 +1922,7 @@ static struct clk mcspi2_ick = { | |||
1917 | 1922 | ||
1918 | static struct clk mcspi1_ick = { | 1923 | static struct clk mcspi1_ick = { |
1919 | .name = "mcspi1_ick", | 1924 | .name = "mcspi1_ick", |
1920 | .ops = &clkops_omap2_dflt_wait, | 1925 | .ops = &clkops_omap2_iclk_dflt_wait, |
1921 | .parent = &core_l4_ick, | 1926 | .parent = &core_l4_ick, |
1922 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1927 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1923 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1928 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
@@ -1927,7 +1932,7 @@ static struct clk mcspi1_ick = { | |||
1927 | 1932 | ||
1928 | static struct clk i2c3_ick = { | 1933 | static struct clk i2c3_ick = { |
1929 | .name = "i2c3_ick", | 1934 | .name = "i2c3_ick", |
1930 | .ops = &clkops_omap2_dflt_wait, | 1935 | .ops = &clkops_omap2_iclk_dflt_wait, |
1931 | .parent = &core_l4_ick, | 1936 | .parent = &core_l4_ick, |
1932 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1937 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1933 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1938 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
@@ -1937,7 +1942,7 @@ static struct clk i2c3_ick = { | |||
1937 | 1942 | ||
1938 | static struct clk i2c2_ick = { | 1943 | static struct clk i2c2_ick = { |
1939 | .name = "i2c2_ick", | 1944 | .name = "i2c2_ick", |
1940 | .ops = &clkops_omap2_dflt_wait, | 1945 | .ops = &clkops_omap2_iclk_dflt_wait, |
1941 | .parent = &core_l4_ick, | 1946 | .parent = &core_l4_ick, |
1942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1947 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1943 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1948 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
@@ -1947,7 +1952,7 @@ static struct clk i2c2_ick = { | |||
1947 | 1952 | ||
1948 | static struct clk i2c1_ick = { | 1953 | static struct clk i2c1_ick = { |
1949 | .name = "i2c1_ick", | 1954 | .name = "i2c1_ick", |
1950 | .ops = &clkops_omap2_dflt_wait, | 1955 | .ops = &clkops_omap2_iclk_dflt_wait, |
1951 | .parent = &core_l4_ick, | 1956 | .parent = &core_l4_ick, |
1952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1957 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1953 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1958 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
@@ -1957,7 +1962,7 @@ static struct clk i2c1_ick = { | |||
1957 | 1962 | ||
1958 | static struct clk uart2_ick = { | 1963 | static struct clk uart2_ick = { |
1959 | .name = "uart2_ick", | 1964 | .name = "uart2_ick", |
1960 | .ops = &clkops_omap2_dflt_wait, | 1965 | .ops = &clkops_omap2_iclk_dflt_wait, |
1961 | .parent = &core_l4_ick, | 1966 | .parent = &core_l4_ick, |
1962 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1967 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1963 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | 1968 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
@@ -1967,7 +1972,7 @@ static struct clk uart2_ick = { | |||
1967 | 1972 | ||
1968 | static struct clk uart1_ick = { | 1973 | static struct clk uart1_ick = { |
1969 | .name = "uart1_ick", | 1974 | .name = "uart1_ick", |
1970 | .ops = &clkops_omap2_dflt_wait, | 1975 | .ops = &clkops_omap2_iclk_dflt_wait, |
1971 | .parent = &core_l4_ick, | 1976 | .parent = &core_l4_ick, |
1972 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1977 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1973 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | 1978 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
@@ -1977,7 +1982,7 @@ static struct clk uart1_ick = { | |||
1977 | 1982 | ||
1978 | static struct clk gpt11_ick = { | 1983 | static struct clk gpt11_ick = { |
1979 | .name = "gpt11_ick", | 1984 | .name = "gpt11_ick", |
1980 | .ops = &clkops_omap2_dflt_wait, | 1985 | .ops = &clkops_omap2_iclk_dflt_wait, |
1981 | .parent = &core_l4_ick, | 1986 | .parent = &core_l4_ick, |
1982 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1987 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1983 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | 1988 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
@@ -1987,7 +1992,7 @@ static struct clk gpt11_ick = { | |||
1987 | 1992 | ||
1988 | static struct clk gpt10_ick = { | 1993 | static struct clk gpt10_ick = { |
1989 | .name = "gpt10_ick", | 1994 | .name = "gpt10_ick", |
1990 | .ops = &clkops_omap2_dflt_wait, | 1995 | .ops = &clkops_omap2_iclk_dflt_wait, |
1991 | .parent = &core_l4_ick, | 1996 | .parent = &core_l4_ick, |
1992 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1997 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1993 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | 1998 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
@@ -1997,7 +2002,7 @@ static struct clk gpt10_ick = { | |||
1997 | 2002 | ||
1998 | static struct clk mcbsp5_ick = { | 2003 | static struct clk mcbsp5_ick = { |
1999 | .name = "mcbsp5_ick", | 2004 | .name = "mcbsp5_ick", |
2000 | .ops = &clkops_omap2_dflt_wait, | 2005 | .ops = &clkops_omap2_iclk_dflt_wait, |
2001 | .parent = &core_l4_ick, | 2006 | .parent = &core_l4_ick, |
2002 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2007 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2003 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 2008 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
@@ -2007,7 +2012,7 @@ static struct clk mcbsp5_ick = { | |||
2007 | 2012 | ||
2008 | static struct clk mcbsp1_ick = { | 2013 | static struct clk mcbsp1_ick = { |
2009 | .name = "mcbsp1_ick", | 2014 | .name = "mcbsp1_ick", |
2010 | .ops = &clkops_omap2_dflt_wait, | 2015 | .ops = &clkops_omap2_iclk_dflt_wait, |
2011 | .parent = &core_l4_ick, | 2016 | .parent = &core_l4_ick, |
2012 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2017 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2013 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 2018 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
@@ -2017,7 +2022,7 @@ static struct clk mcbsp1_ick = { | |||
2017 | 2022 | ||
2018 | static struct clk fac_ick = { | 2023 | static struct clk fac_ick = { |
2019 | .name = "fac_ick", | 2024 | .name = "fac_ick", |
2020 | .ops = &clkops_omap2_dflt_wait, | 2025 | .ops = &clkops_omap2_iclk_dflt_wait, |
2021 | .parent = &core_l4_ick, | 2026 | .parent = &core_l4_ick, |
2022 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2027 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2023 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | 2028 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, |
@@ -2027,7 +2032,7 @@ static struct clk fac_ick = { | |||
2027 | 2032 | ||
2028 | static struct clk mailboxes_ick = { | 2033 | static struct clk mailboxes_ick = { |
2029 | .name = "mailboxes_ick", | 2034 | .name = "mailboxes_ick", |
2030 | .ops = &clkops_omap2_dflt_wait, | 2035 | .ops = &clkops_omap2_iclk_dflt_wait, |
2031 | .parent = &core_l4_ick, | 2036 | .parent = &core_l4_ick, |
2032 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2037 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2033 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | 2038 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
@@ -2037,7 +2042,7 @@ static struct clk mailboxes_ick = { | |||
2037 | 2042 | ||
2038 | static struct clk omapctrl_ick = { | 2043 | static struct clk omapctrl_ick = { |
2039 | .name = "omapctrl_ick", | 2044 | .name = "omapctrl_ick", |
2040 | .ops = &clkops_omap2_dflt_wait, | 2045 | .ops = &clkops_omap2_iclk_dflt_wait, |
2041 | .parent = &core_l4_ick, | 2046 | .parent = &core_l4_ick, |
2042 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2043 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | 2048 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
@@ -2057,7 +2062,7 @@ static struct clk ssi_l4_ick = { | |||
2057 | 2062 | ||
2058 | static struct clk ssi_ick_3430es1 = { | 2063 | static struct clk ssi_ick_3430es1 = { |
2059 | .name = "ssi_ick", | 2064 | .name = "ssi_ick", |
2060 | .ops = &clkops_omap2_dflt, | 2065 | .ops = &clkops_omap2_iclk_dflt, |
2061 | .parent = &ssi_l4_ick, | 2066 | .parent = &ssi_l4_ick, |
2062 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2067 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2063 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | 2068 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
@@ -2067,7 +2072,7 @@ static struct clk ssi_ick_3430es1 = { | |||
2067 | 2072 | ||
2068 | static struct clk ssi_ick_3430es2 = { | 2073 | static struct clk ssi_ick_3430es2 = { |
2069 | .name = "ssi_ick", | 2074 | .name = "ssi_ick", |
2070 | .ops = &clkops_omap3430es2_ssi_wait, | 2075 | .ops = &clkops_omap3430es2_iclk_ssi_wait, |
2071 | .parent = &ssi_l4_ick, | 2076 | .parent = &ssi_l4_ick, |
2072 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2077 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2073 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | 2078 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
@@ -2085,7 +2090,7 @@ static const struct clksel usb_l4_clksel[] = { | |||
2085 | 2090 | ||
2086 | static struct clk usb_l4_ick = { | 2091 | static struct clk usb_l4_ick = { |
2087 | .name = "usb_l4_ick", | 2092 | .name = "usb_l4_ick", |
2088 | .ops = &clkops_omap2_dflt_wait, | 2093 | .ops = &clkops_omap2_iclk_dflt_wait, |
2089 | .parent = &l4_ick, | 2094 | .parent = &l4_ick, |
2090 | .init = &omap2_init_clksel_parent, | 2095 | .init = &omap2_init_clksel_parent, |
2091 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2096 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
@@ -2107,7 +2112,7 @@ static struct clk security_l4_ick2 = { | |||
2107 | 2112 | ||
2108 | static struct clk aes1_ick = { | 2113 | static struct clk aes1_ick = { |
2109 | .name = "aes1_ick", | 2114 | .name = "aes1_ick", |
2110 | .ops = &clkops_omap2_dflt_wait, | 2115 | .ops = &clkops_omap2_iclk_dflt_wait, |
2111 | .parent = &security_l4_ick2, | 2116 | .parent = &security_l4_ick2, |
2112 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2117 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2113 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | 2118 | .enable_bit = OMAP3430_EN_AES1_SHIFT, |
@@ -2116,7 +2121,7 @@ static struct clk aes1_ick = { | |||
2116 | 2121 | ||
2117 | static struct clk rng_ick = { | 2122 | static struct clk rng_ick = { |
2118 | .name = "rng_ick", | 2123 | .name = "rng_ick", |
2119 | .ops = &clkops_omap2_dflt_wait, | 2124 | .ops = &clkops_omap2_iclk_dflt_wait, |
2120 | .parent = &security_l4_ick2, | 2125 | .parent = &security_l4_ick2, |
2121 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2126 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2122 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | 2127 | .enable_bit = OMAP3430_EN_RNG_SHIFT, |
@@ -2125,7 +2130,7 @@ static struct clk rng_ick = { | |||
2125 | 2130 | ||
2126 | static struct clk sha11_ick = { | 2131 | static struct clk sha11_ick = { |
2127 | .name = "sha11_ick", | 2132 | .name = "sha11_ick", |
2128 | .ops = &clkops_omap2_dflt_wait, | 2133 | .ops = &clkops_omap2_iclk_dflt_wait, |
2129 | .parent = &security_l4_ick2, | 2134 | .parent = &security_l4_ick2, |
2130 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2135 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2131 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | 2136 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, |
@@ -2134,7 +2139,7 @@ static struct clk sha11_ick = { | |||
2134 | 2139 | ||
2135 | static struct clk des1_ick = { | 2140 | static struct clk des1_ick = { |
2136 | .name = "des1_ick", | 2141 | .name = "des1_ick", |
2137 | .ops = &clkops_omap2_dflt_wait, | 2142 | .ops = &clkops_omap2_iclk_dflt_wait, |
2138 | .parent = &security_l4_ick2, | 2143 | .parent = &security_l4_ick2, |
2139 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2144 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2140 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | 2145 | .enable_bit = OMAP3430_EN_DES1_SHIFT, |
@@ -2195,7 +2200,7 @@ static struct clk dss2_alwon_fck = { | |||
2195 | static struct clk dss_ick_3430es1 = { | 2200 | static struct clk dss_ick_3430es1 = { |
2196 | /* Handles both L3 and L4 clocks */ | 2201 | /* Handles both L3 and L4 clocks */ |
2197 | .name = "dss_ick", | 2202 | .name = "dss_ick", |
2198 | .ops = &clkops_omap2_dflt, | 2203 | .ops = &clkops_omap2_iclk_dflt, |
2199 | .parent = &l4_ick, | 2204 | .parent = &l4_ick, |
2200 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2205 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2201 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2206 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
@@ -2206,7 +2211,7 @@ static struct clk dss_ick_3430es1 = { | |||
2206 | static struct clk dss_ick_3430es2 = { | 2211 | static struct clk dss_ick_3430es2 = { |
2207 | /* Handles both L3 and L4 clocks */ | 2212 | /* Handles both L3 and L4 clocks */ |
2208 | .name = "dss_ick", | 2213 | .name = "dss_ick", |
2209 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | 2214 | .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, |
2210 | .parent = &l4_ick, | 2215 | .parent = &l4_ick, |
2211 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2216 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2212 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2217 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
@@ -2229,7 +2234,7 @@ static struct clk cam_mclk = { | |||
2229 | static struct clk cam_ick = { | 2234 | static struct clk cam_ick = { |
2230 | /* Handles both L3 and L4 clocks */ | 2235 | /* Handles both L3 and L4 clocks */ |
2231 | .name = "cam_ick", | 2236 | .name = "cam_ick", |
2232 | .ops = &clkops_omap2_dflt, | 2237 | .ops = &clkops_omap2_iclk_dflt, |
2233 | .parent = &l4_ick, | 2238 | .parent = &l4_ick, |
2234 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | 2239 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
2235 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2240 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
@@ -2272,7 +2277,7 @@ static struct clk usbhost_48m_fck = { | |||
2272 | static struct clk usbhost_ick = { | 2277 | static struct clk usbhost_ick = { |
2273 | /* Handles both L3 and L4 clocks */ | 2278 | /* Handles both L3 and L4 clocks */ |
2274 | .name = "usbhost_ick", | 2279 | .name = "usbhost_ick", |
2275 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | 2280 | .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, |
2276 | .parent = &l4_ick, | 2281 | .parent = &l4_ick, |
2277 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | 2282 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
2278 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | 2283 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
@@ -2372,7 +2377,7 @@ static struct clk wkup_l4_ick = { | |||
2372 | /* Never specifically named in the TRM, so we have to infer a likely name */ | 2377 | /* Never specifically named in the TRM, so we have to infer a likely name */ |
2373 | static struct clk usim_ick = { | 2378 | static struct clk usim_ick = { |
2374 | .name = "usim_ick", | 2379 | .name = "usim_ick", |
2375 | .ops = &clkops_omap2_dflt_wait, | 2380 | .ops = &clkops_omap2_iclk_dflt_wait, |
2376 | .parent = &wkup_l4_ick, | 2381 | .parent = &wkup_l4_ick, |
2377 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2382 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2378 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | 2383 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
@@ -2382,7 +2387,7 @@ static struct clk usim_ick = { | |||
2382 | 2387 | ||
2383 | static struct clk wdt2_ick = { | 2388 | static struct clk wdt2_ick = { |
2384 | .name = "wdt2_ick", | 2389 | .name = "wdt2_ick", |
2385 | .ops = &clkops_omap2_dflt_wait, | 2390 | .ops = &clkops_omap2_iclk_dflt_wait, |
2386 | .parent = &wkup_l4_ick, | 2391 | .parent = &wkup_l4_ick, |
2387 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2392 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2388 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | 2393 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
@@ -2392,7 +2397,7 @@ static struct clk wdt2_ick = { | |||
2392 | 2397 | ||
2393 | static struct clk wdt1_ick = { | 2398 | static struct clk wdt1_ick = { |
2394 | .name = "wdt1_ick", | 2399 | .name = "wdt1_ick", |
2395 | .ops = &clkops_omap2_dflt_wait, | 2400 | .ops = &clkops_omap2_iclk_dflt_wait, |
2396 | .parent = &wkup_l4_ick, | 2401 | .parent = &wkup_l4_ick, |
2397 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2402 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2398 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | 2403 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, |
@@ -2402,7 +2407,7 @@ static struct clk wdt1_ick = { | |||
2402 | 2407 | ||
2403 | static struct clk gpio1_ick = { | 2408 | static struct clk gpio1_ick = { |
2404 | .name = "gpio1_ick", | 2409 | .name = "gpio1_ick", |
2405 | .ops = &clkops_omap2_dflt_wait, | 2410 | .ops = &clkops_omap2_iclk_dflt_wait, |
2406 | .parent = &wkup_l4_ick, | 2411 | .parent = &wkup_l4_ick, |
2407 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2412 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2408 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | 2413 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
@@ -2412,7 +2417,7 @@ static struct clk gpio1_ick = { | |||
2412 | 2417 | ||
2413 | static struct clk omap_32ksync_ick = { | 2418 | static struct clk omap_32ksync_ick = { |
2414 | .name = "omap_32ksync_ick", | 2419 | .name = "omap_32ksync_ick", |
2415 | .ops = &clkops_omap2_dflt_wait, | 2420 | .ops = &clkops_omap2_iclk_dflt_wait, |
2416 | .parent = &wkup_l4_ick, | 2421 | .parent = &wkup_l4_ick, |
2417 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2422 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2418 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | 2423 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, |
@@ -2423,7 +2428,7 @@ static struct clk omap_32ksync_ick = { | |||
2423 | /* XXX This clock no longer exists in 3430 TRM rev F */ | 2428 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
2424 | static struct clk gpt12_ick = { | 2429 | static struct clk gpt12_ick = { |
2425 | .name = "gpt12_ick", | 2430 | .name = "gpt12_ick", |
2426 | .ops = &clkops_omap2_dflt_wait, | 2431 | .ops = &clkops_omap2_iclk_dflt_wait, |
2427 | .parent = &wkup_l4_ick, | 2432 | .parent = &wkup_l4_ick, |
2428 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2433 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2429 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | 2434 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, |
@@ -2433,7 +2438,7 @@ static struct clk gpt12_ick = { | |||
2433 | 2438 | ||
2434 | static struct clk gpt1_ick = { | 2439 | static struct clk gpt1_ick = { |
2435 | .name = "gpt1_ick", | 2440 | .name = "gpt1_ick", |
2436 | .ops = &clkops_omap2_dflt_wait, | 2441 | .ops = &clkops_omap2_iclk_dflt_wait, |
2437 | .parent = &wkup_l4_ick, | 2442 | .parent = &wkup_l4_ick, |
2438 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2443 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2439 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | 2444 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
@@ -2663,7 +2668,7 @@ static struct clk per_l4_ick = { | |||
2663 | 2668 | ||
2664 | static struct clk gpio6_ick = { | 2669 | static struct clk gpio6_ick = { |
2665 | .name = "gpio6_ick", | 2670 | .name = "gpio6_ick", |
2666 | .ops = &clkops_omap2_dflt_wait, | 2671 | .ops = &clkops_omap2_iclk_dflt_wait, |
2667 | .parent = &per_l4_ick, | 2672 | .parent = &per_l4_ick, |
2668 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2673 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2669 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | 2674 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
@@ -2673,7 +2678,7 @@ static struct clk gpio6_ick = { | |||
2673 | 2678 | ||
2674 | static struct clk gpio5_ick = { | 2679 | static struct clk gpio5_ick = { |
2675 | .name = "gpio5_ick", | 2680 | .name = "gpio5_ick", |
2676 | .ops = &clkops_omap2_dflt_wait, | 2681 | .ops = &clkops_omap2_iclk_dflt_wait, |
2677 | .parent = &per_l4_ick, | 2682 | .parent = &per_l4_ick, |
2678 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2683 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2679 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | 2684 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
@@ -2683,7 +2688,7 @@ static struct clk gpio5_ick = { | |||
2683 | 2688 | ||
2684 | static struct clk gpio4_ick = { | 2689 | static struct clk gpio4_ick = { |
2685 | .name = "gpio4_ick", | 2690 | .name = "gpio4_ick", |
2686 | .ops = &clkops_omap2_dflt_wait, | 2691 | .ops = &clkops_omap2_iclk_dflt_wait, |
2687 | .parent = &per_l4_ick, | 2692 | .parent = &per_l4_ick, |
2688 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2693 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2689 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | 2694 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
@@ -2693,7 +2698,7 @@ static struct clk gpio4_ick = { | |||
2693 | 2698 | ||
2694 | static struct clk gpio3_ick = { | 2699 | static struct clk gpio3_ick = { |
2695 | .name = "gpio3_ick", | 2700 | .name = "gpio3_ick", |
2696 | .ops = &clkops_omap2_dflt_wait, | 2701 | .ops = &clkops_omap2_iclk_dflt_wait, |
2697 | .parent = &per_l4_ick, | 2702 | .parent = &per_l4_ick, |
2698 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2703 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2699 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | 2704 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
@@ -2703,7 +2708,7 @@ static struct clk gpio3_ick = { | |||
2703 | 2708 | ||
2704 | static struct clk gpio2_ick = { | 2709 | static struct clk gpio2_ick = { |
2705 | .name = "gpio2_ick", | 2710 | .name = "gpio2_ick", |
2706 | .ops = &clkops_omap2_dflt_wait, | 2711 | .ops = &clkops_omap2_iclk_dflt_wait, |
2707 | .parent = &per_l4_ick, | 2712 | .parent = &per_l4_ick, |
2708 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2713 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2709 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | 2714 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
@@ -2713,7 +2718,7 @@ static struct clk gpio2_ick = { | |||
2713 | 2718 | ||
2714 | static struct clk wdt3_ick = { | 2719 | static struct clk wdt3_ick = { |
2715 | .name = "wdt3_ick", | 2720 | .name = "wdt3_ick", |
2716 | .ops = &clkops_omap2_dflt_wait, | 2721 | .ops = &clkops_omap2_iclk_dflt_wait, |
2717 | .parent = &per_l4_ick, | 2722 | .parent = &per_l4_ick, |
2718 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2723 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2719 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | 2724 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
@@ -2723,7 +2728,7 @@ static struct clk wdt3_ick = { | |||
2723 | 2728 | ||
2724 | static struct clk uart3_ick = { | 2729 | static struct clk uart3_ick = { |
2725 | .name = "uart3_ick", | 2730 | .name = "uart3_ick", |
2726 | .ops = &clkops_omap2_dflt_wait, | 2731 | .ops = &clkops_omap2_iclk_dflt_wait, |
2727 | .parent = &per_l4_ick, | 2732 | .parent = &per_l4_ick, |
2728 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2733 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2729 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | 2734 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
@@ -2733,7 +2738,7 @@ static struct clk uart3_ick = { | |||
2733 | 2738 | ||
2734 | static struct clk uart4_ick = { | 2739 | static struct clk uart4_ick = { |
2735 | .name = "uart4_ick", | 2740 | .name = "uart4_ick", |
2736 | .ops = &clkops_omap2_dflt_wait, | 2741 | .ops = &clkops_omap2_iclk_dflt_wait, |
2737 | .parent = &per_l4_ick, | 2742 | .parent = &per_l4_ick, |
2738 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2743 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2739 | .enable_bit = OMAP3630_EN_UART4_SHIFT, | 2744 | .enable_bit = OMAP3630_EN_UART4_SHIFT, |
@@ -2743,7 +2748,7 @@ static struct clk uart4_ick = { | |||
2743 | 2748 | ||
2744 | static struct clk gpt9_ick = { | 2749 | static struct clk gpt9_ick = { |
2745 | .name = "gpt9_ick", | 2750 | .name = "gpt9_ick", |
2746 | .ops = &clkops_omap2_dflt_wait, | 2751 | .ops = &clkops_omap2_iclk_dflt_wait, |
2747 | .parent = &per_l4_ick, | 2752 | .parent = &per_l4_ick, |
2748 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2753 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2749 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | 2754 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
@@ -2753,7 +2758,7 @@ static struct clk gpt9_ick = { | |||
2753 | 2758 | ||
2754 | static struct clk gpt8_ick = { | 2759 | static struct clk gpt8_ick = { |
2755 | .name = "gpt8_ick", | 2760 | .name = "gpt8_ick", |
2756 | .ops = &clkops_omap2_dflt_wait, | 2761 | .ops = &clkops_omap2_iclk_dflt_wait, |
2757 | .parent = &per_l4_ick, | 2762 | .parent = &per_l4_ick, |
2758 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2763 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2759 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | 2764 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
@@ -2763,7 +2768,7 @@ static struct clk gpt8_ick = { | |||
2763 | 2768 | ||
2764 | static struct clk gpt7_ick = { | 2769 | static struct clk gpt7_ick = { |
2765 | .name = "gpt7_ick", | 2770 | .name = "gpt7_ick", |
2766 | .ops = &clkops_omap2_dflt_wait, | 2771 | .ops = &clkops_omap2_iclk_dflt_wait, |
2767 | .parent = &per_l4_ick, | 2772 | .parent = &per_l4_ick, |
2768 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2773 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2769 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | 2774 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
@@ -2773,7 +2778,7 @@ static struct clk gpt7_ick = { | |||
2773 | 2778 | ||
2774 | static struct clk gpt6_ick = { | 2779 | static struct clk gpt6_ick = { |
2775 | .name = "gpt6_ick", | 2780 | .name = "gpt6_ick", |
2776 | .ops = &clkops_omap2_dflt_wait, | 2781 | .ops = &clkops_omap2_iclk_dflt_wait, |
2777 | .parent = &per_l4_ick, | 2782 | .parent = &per_l4_ick, |
2778 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2783 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2779 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | 2784 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
@@ -2783,7 +2788,7 @@ static struct clk gpt6_ick = { | |||
2783 | 2788 | ||
2784 | static struct clk gpt5_ick = { | 2789 | static struct clk gpt5_ick = { |
2785 | .name = "gpt5_ick", | 2790 | .name = "gpt5_ick", |
2786 | .ops = &clkops_omap2_dflt_wait, | 2791 | .ops = &clkops_omap2_iclk_dflt_wait, |
2787 | .parent = &per_l4_ick, | 2792 | .parent = &per_l4_ick, |
2788 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2793 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2789 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | 2794 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
@@ -2793,7 +2798,7 @@ static struct clk gpt5_ick = { | |||
2793 | 2798 | ||
2794 | static struct clk gpt4_ick = { | 2799 | static struct clk gpt4_ick = { |
2795 | .name = "gpt4_ick", | 2800 | .name = "gpt4_ick", |
2796 | .ops = &clkops_omap2_dflt_wait, | 2801 | .ops = &clkops_omap2_iclk_dflt_wait, |
2797 | .parent = &per_l4_ick, | 2802 | .parent = &per_l4_ick, |
2798 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2803 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2799 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | 2804 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
@@ -2803,7 +2808,7 @@ static struct clk gpt4_ick = { | |||
2803 | 2808 | ||
2804 | static struct clk gpt3_ick = { | 2809 | static struct clk gpt3_ick = { |
2805 | .name = "gpt3_ick", | 2810 | .name = "gpt3_ick", |
2806 | .ops = &clkops_omap2_dflt_wait, | 2811 | .ops = &clkops_omap2_iclk_dflt_wait, |
2807 | .parent = &per_l4_ick, | 2812 | .parent = &per_l4_ick, |
2808 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2813 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2809 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | 2814 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
@@ -2813,7 +2818,7 @@ static struct clk gpt3_ick = { | |||
2813 | 2818 | ||
2814 | static struct clk gpt2_ick = { | 2819 | static struct clk gpt2_ick = { |
2815 | .name = "gpt2_ick", | 2820 | .name = "gpt2_ick", |
2816 | .ops = &clkops_omap2_dflt_wait, | 2821 | .ops = &clkops_omap2_iclk_dflt_wait, |
2817 | .parent = &per_l4_ick, | 2822 | .parent = &per_l4_ick, |
2818 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2823 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2819 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | 2824 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
@@ -2823,7 +2828,7 @@ static struct clk gpt2_ick = { | |||
2823 | 2828 | ||
2824 | static struct clk mcbsp2_ick = { | 2829 | static struct clk mcbsp2_ick = { |
2825 | .name = "mcbsp2_ick", | 2830 | .name = "mcbsp2_ick", |
2826 | .ops = &clkops_omap2_dflt_wait, | 2831 | .ops = &clkops_omap2_iclk_dflt_wait, |
2827 | .parent = &per_l4_ick, | 2832 | .parent = &per_l4_ick, |
2828 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2833 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2829 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2834 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
@@ -2833,7 +2838,7 @@ static struct clk mcbsp2_ick = { | |||
2833 | 2838 | ||
2834 | static struct clk mcbsp3_ick = { | 2839 | static struct clk mcbsp3_ick = { |
2835 | .name = "mcbsp3_ick", | 2840 | .name = "mcbsp3_ick", |
2836 | .ops = &clkops_omap2_dflt_wait, | 2841 | .ops = &clkops_omap2_iclk_dflt_wait, |
2837 | .parent = &per_l4_ick, | 2842 | .parent = &per_l4_ick, |
2838 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2843 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2839 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2844 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
@@ -2843,7 +2848,7 @@ static struct clk mcbsp3_ick = { | |||
2843 | 2848 | ||
2844 | static struct clk mcbsp4_ick = { | 2849 | static struct clk mcbsp4_ick = { |
2845 | .name = "mcbsp4_ick", | 2850 | .name = "mcbsp4_ick", |
2846 | .ops = &clkops_omap2_dflt_wait, | 2851 | .ops = &clkops_omap2_iclk_dflt_wait, |
2847 | .parent = &per_l4_ick, | 2852 | .parent = &per_l4_ick, |
2848 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2853 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
2849 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2854 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
@@ -3186,7 +3191,7 @@ static struct clk vpfe_fck = { | |||
3186 | */ | 3191 | */ |
3187 | static struct clk uart4_ick_am35xx = { | 3192 | static struct clk uart4_ick_am35xx = { |
3188 | .name = "uart4_ick", | 3193 | .name = "uart4_ick", |
3189 | .ops = &clkops_omap2_dflt_wait, | 3194 | .ops = &clkops_omap2_iclk_dflt_wait, |
3190 | .parent = &core_l4_ick, | 3195 | .parent = &core_l4_ick, |
3191 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 3196 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
3192 | .enable_bit = AM35XX_EN_UART4_SHIFT, | 3197 | .enable_bit = AM35XX_EN_UART4_SHIFT, |