diff options
author | Rajendra Nayak <rnayak@ti.com> | 2012-04-27 06:23:48 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2012-11-12 21:10:18 -0500 |
commit | b4777a21381fd1f87be8c606a616b7f97f485d2b (patch) | |
tree | af45be72d14dde6fc899ac2ad5f9984f1bfa5cd5 /arch/arm/mach-omap2/clock3xxx.c | |
parent | 32cc002116b866151ca24c6e9110ba8a93754753 (diff) |
ARM: OMAP3: clock: Convert to common clk
Convert all OMAP3 specific platform files to use COMMON clk
and keep all the changes under the CONFIG_COMMON_CLK macro check
so it does not break any existing code. At a later point switch
to COMMON clk and get rid of all old/legacy code.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx.c')
-rw-r--r-- | arch/arm/mach-omap2/clock3xxx.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 3e8aca2b1b61..a6f75cd85327 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c | |||
@@ -38,8 +38,12 @@ | |||
38 | 38 | ||
39 | /* needed by omap3_core_dpll_m2_set_rate() */ | 39 | /* needed by omap3_core_dpll_m2_set_rate() */ |
40 | struct clk *sdrc_ick_p, *arm_fck_p; | 40 | struct clk *sdrc_ick_p, *arm_fck_p; |
41 | 41 | #ifdef CONFIG_COMMON_CLK | |
42 | int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, | ||
43 | unsigned long parent_rate) | ||
44 | #else | ||
42 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | 45 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) |
46 | #endif | ||
43 | { | 47 | { |
44 | /* | 48 | /* |
45 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | 49 | * According to the 12-5 CDP code from TI, "Limitation 2.5" |
@@ -51,7 +55,11 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | |||
51 | return -EINVAL; | 55 | return -EINVAL; |
52 | } | 56 | } |
53 | 57 | ||
58 | #ifdef CONFIG_COMMON_CLK | ||
59 | return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); | ||
60 | #else | ||
54 | return omap3_noncore_dpll_set_rate(clk, rate); | 61 | return omap3_noncore_dpll_set_rate(clk, rate); |
62 | #endif | ||
55 | } | 63 | } |
56 | 64 | ||
57 | void __init omap3_clk_lock_dpll5(void) | 65 | void __init omap3_clk_lock_dpll5(void) |