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authorPaul Walmsley <paul@pwsan.com>2010-02-23 00:09:19 -0500
committerPaul Walmsley <paul@pwsan.com>2010-02-24 14:16:13 -0500
commitb92c170d019db7554db95380d2e1dfb3a368e350 (patch)
tree2ab2743375335d56683b83cea48876eb37a43b81 /arch/arm/mach-omap2/clock34xx_data.c
parentf71eddb1582f5c53ed4bfc365a2acce94aca88cc (diff)
OMAP clock: drop .id field; ensure each clock has a unique name
After the clkdev conversion, the struct clk.id field became superfluous, so, drop it. Bring the clock names closer to the TRMs and ensure they are unique for debugfs. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock34xx_data.c88
1 files changed, 30 insertions, 58 deletions
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index 94f603b16c5e..995d5d4c897d 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -1505,9 +1505,8 @@ static struct clk core_96m_fck = {
1505}; 1505};
1506 1506
1507static struct clk mmchs3_fck = { 1507static struct clk mmchs3_fck = {
1508 .name = "mmchs_fck", 1508 .name = "mmchs3_fck",
1509 .ops = &clkops_omap2_dflt_wait, 1509 .ops = &clkops_omap2_dflt_wait,
1510 .id = 2,
1511 .parent = &core_96m_fck, 1510 .parent = &core_96m_fck,
1512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1513 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1512 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1516,9 +1515,8 @@ static struct clk mmchs3_fck = {
1516}; 1515};
1517 1516
1518static struct clk mmchs2_fck = { 1517static struct clk mmchs2_fck = {
1519 .name = "mmchs_fck", 1518 .name = "mmchs2_fck",
1520 .ops = &clkops_omap2_dflt_wait, 1519 .ops = &clkops_omap2_dflt_wait,
1521 .id = 1,
1522 .parent = &core_96m_fck, 1520 .parent = &core_96m_fck,
1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1521 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1522 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1537,7 +1535,7 @@ static struct clk mspro_fck = {
1537}; 1535};
1538 1536
1539static struct clk mmchs1_fck = { 1537static struct clk mmchs1_fck = {
1540 .name = "mmchs_fck", 1538 .name = "mmchs1_fck",
1541 .ops = &clkops_omap2_dflt_wait, 1539 .ops = &clkops_omap2_dflt_wait,
1542 .parent = &core_96m_fck, 1540 .parent = &core_96m_fck,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1541 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1547,9 +1545,8 @@ static struct clk mmchs1_fck = {
1547}; 1545};
1548 1546
1549static struct clk i2c3_fck = { 1547static struct clk i2c3_fck = {
1550 .name = "i2c_fck", 1548 .name = "i2c3_fck",
1551 .ops = &clkops_omap2_dflt_wait, 1549 .ops = &clkops_omap2_dflt_wait,
1552 .id = 3,
1553 .parent = &core_96m_fck, 1550 .parent = &core_96m_fck,
1554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1551 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1555 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1552 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
@@ -1558,9 +1555,8 @@ static struct clk i2c3_fck = {
1558}; 1555};
1559 1556
1560static struct clk i2c2_fck = { 1557static struct clk i2c2_fck = {
1561 .name = "i2c_fck", 1558 .name = "i2c2_fck",
1562 .ops = &clkops_omap2_dflt_wait, 1559 .ops = &clkops_omap2_dflt_wait,
1563 .id = 2,
1564 .parent = &core_96m_fck, 1560 .parent = &core_96m_fck,
1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1562 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
@@ -1569,9 +1565,8 @@ static struct clk i2c2_fck = {
1569}; 1565};
1570 1566
1571static struct clk i2c1_fck = { 1567static struct clk i2c1_fck = {
1572 .name = "i2c_fck", 1568 .name = "i2c1_fck",
1573 .ops = &clkops_omap2_dflt_wait, 1569 .ops = &clkops_omap2_dflt_wait,
1574 .id = 1,
1575 .parent = &core_96m_fck, 1570 .parent = &core_96m_fck,
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1572 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
@@ -1600,9 +1595,8 @@ static const struct clksel mcbsp_15_clksel[] = {
1600}; 1595};
1601 1596
1602static struct clk mcbsp5_fck = { 1597static struct clk mcbsp5_fck = {
1603 .name = "mcbsp_fck", 1598 .name = "mcbsp5_fck",
1604 .ops = &clkops_omap2_dflt_wait, 1599 .ops = &clkops_omap2_dflt_wait,
1605 .id = 5,
1606 .init = &omap2_init_clksel_parent, 1600 .init = &omap2_init_clksel_parent,
1607 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1608 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1602 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1614,9 +1608,8 @@ static struct clk mcbsp5_fck = {
1614}; 1608};
1615 1609
1616static struct clk mcbsp1_fck = { 1610static struct clk mcbsp1_fck = {
1617 .name = "mcbsp_fck", 1611 .name = "mcbsp1_fck",
1618 .ops = &clkops_omap2_dflt_wait, 1612 .ops = &clkops_omap2_dflt_wait,
1619 .id = 1,
1620 .init = &omap2_init_clksel_parent, 1613 .init = &omap2_init_clksel_parent,
1621 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1614 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1622 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1615 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -1638,9 +1631,8 @@ static struct clk core_48m_fck = {
1638}; 1631};
1639 1632
1640static struct clk mcspi4_fck = { 1633static struct clk mcspi4_fck = {
1641 .name = "mcspi_fck", 1634 .name = "mcspi4_fck",
1642 .ops = &clkops_omap2_dflt_wait, 1635 .ops = &clkops_omap2_dflt_wait,
1643 .id = 4,
1644 .parent = &core_48m_fck, 1636 .parent = &core_48m_fck,
1645 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1646 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1638 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1648,9 +1640,8 @@ static struct clk mcspi4_fck = {
1648}; 1640};
1649 1641
1650static struct clk mcspi3_fck = { 1642static struct clk mcspi3_fck = {
1651 .name = "mcspi_fck", 1643 .name = "mcspi3_fck",
1652 .ops = &clkops_omap2_dflt_wait, 1644 .ops = &clkops_omap2_dflt_wait,
1653 .id = 3,
1654 .parent = &core_48m_fck, 1645 .parent = &core_48m_fck,
1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1656 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1647 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1658,9 +1649,8 @@ static struct clk mcspi3_fck = {
1658}; 1649};
1659 1650
1660static struct clk mcspi2_fck = { 1651static struct clk mcspi2_fck = {
1661 .name = "mcspi_fck", 1652 .name = "mcspi2_fck",
1662 .ops = &clkops_omap2_dflt_wait, 1653 .ops = &clkops_omap2_dflt_wait,
1663 .id = 2,
1664 .parent = &core_48m_fck, 1654 .parent = &core_48m_fck,
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1666 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1656 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1668,9 +1658,8 @@ static struct clk mcspi2_fck = {
1668}; 1658};
1669 1659
1670static struct clk mcspi1_fck = { 1660static struct clk mcspi1_fck = {
1671 .name = "mcspi_fck", 1661 .name = "mcspi1_fck",
1672 .ops = &clkops_omap2_dflt_wait, 1662 .ops = &clkops_omap2_dflt_wait,
1673 .id = 1,
1674 .parent = &core_48m_fck, 1663 .parent = &core_48m_fck,
1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1664 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1676 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1665 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1879,9 +1868,8 @@ static struct clk usbtll_ick = {
1879}; 1868};
1880 1869
1881static struct clk mmchs3_ick = { 1870static struct clk mmchs3_ick = {
1882 .name = "mmchs_ick", 1871 .name = "mmchs3_ick",
1883 .ops = &clkops_omap2_dflt_wait, 1872 .ops = &clkops_omap2_dflt_wait,
1884 .id = 2,
1885 .parent = &core_l4_ick, 1873 .parent = &core_l4_ick,
1886 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1887 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1875 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1931,9 +1919,8 @@ static struct clk des2_ick = {
1931}; 1919};
1932 1920
1933static struct clk mmchs2_ick = { 1921static struct clk mmchs2_ick = {
1934 .name = "mmchs_ick", 1922 .name = "mmchs2_ick",
1935 .ops = &clkops_omap2_dflt_wait, 1923 .ops = &clkops_omap2_dflt_wait,
1936 .id = 1,
1937 .parent = &core_l4_ick, 1924 .parent = &core_l4_ick,
1938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1926 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1942,7 +1929,7 @@ static struct clk mmchs2_ick = {
1942}; 1929};
1943 1930
1944static struct clk mmchs1_ick = { 1931static struct clk mmchs1_ick = {
1945 .name = "mmchs_ick", 1932 .name = "mmchs1_ick",
1946 .ops = &clkops_omap2_dflt_wait, 1933 .ops = &clkops_omap2_dflt_wait,
1947 .parent = &core_l4_ick, 1934 .parent = &core_l4_ick,
1948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1972,9 +1959,8 @@ static struct clk hdq_ick = {
1972}; 1959};
1973 1960
1974static struct clk mcspi4_ick = { 1961static struct clk mcspi4_ick = {
1975 .name = "mcspi_ick", 1962 .name = "mcspi4_ick",
1976 .ops = &clkops_omap2_dflt_wait, 1963 .ops = &clkops_omap2_dflt_wait,
1977 .id = 4,
1978 .parent = &core_l4_ick, 1964 .parent = &core_l4_ick,
1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1965 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1980 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1966 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1983,9 +1969,8 @@ static struct clk mcspi4_ick = {
1983}; 1969};
1984 1970
1985static struct clk mcspi3_ick = { 1971static struct clk mcspi3_ick = {
1986 .name = "mcspi_ick", 1972 .name = "mcspi3_ick",
1987 .ops = &clkops_omap2_dflt_wait, 1973 .ops = &clkops_omap2_dflt_wait,
1988 .id = 3,
1989 .parent = &core_l4_ick, 1974 .parent = &core_l4_ick,
1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1975 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1991 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1976 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1994,9 +1979,8 @@ static struct clk mcspi3_ick = {
1994}; 1979};
1995 1980
1996static struct clk mcspi2_ick = { 1981static struct clk mcspi2_ick = {
1997 .name = "mcspi_ick", 1982 .name = "mcspi2_ick",
1998 .ops = &clkops_omap2_dflt_wait, 1983 .ops = &clkops_omap2_dflt_wait,
1999 .id = 2,
2000 .parent = &core_l4_ick, 1984 .parent = &core_l4_ick,
2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1985 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2002 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1986 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@@ -2005,9 +1989,8 @@ static struct clk mcspi2_ick = {
2005}; 1989};
2006 1990
2007static struct clk mcspi1_ick = { 1991static struct clk mcspi1_ick = {
2008 .name = "mcspi_ick", 1992 .name = "mcspi1_ick",
2009 .ops = &clkops_omap2_dflt_wait, 1993 .ops = &clkops_omap2_dflt_wait,
2010 .id = 1,
2011 .parent = &core_l4_ick, 1994 .parent = &core_l4_ick,
2012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1995 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2013 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1996 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@@ -2016,9 +1999,8 @@ static struct clk mcspi1_ick = {
2016}; 1999};
2017 2000
2018static struct clk i2c3_ick = { 2001static struct clk i2c3_ick = {
2019 .name = "i2c_ick", 2002 .name = "i2c3_ick",
2020 .ops = &clkops_omap2_dflt_wait, 2003 .ops = &clkops_omap2_dflt_wait,
2021 .id = 3,
2022 .parent = &core_l4_ick, 2004 .parent = &core_l4_ick,
2023 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2005 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2024 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 2006 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
@@ -2027,9 +2009,8 @@ static struct clk i2c3_ick = {
2027}; 2009};
2028 2010
2029static struct clk i2c2_ick = { 2011static struct clk i2c2_ick = {
2030 .name = "i2c_ick", 2012 .name = "i2c2_ick",
2031 .ops = &clkops_omap2_dflt_wait, 2013 .ops = &clkops_omap2_dflt_wait,
2032 .id = 2,
2033 .parent = &core_l4_ick, 2014 .parent = &core_l4_ick,
2034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2035 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 2016 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
@@ -2038,9 +2019,8 @@ static struct clk i2c2_ick = {
2038}; 2019};
2039 2020
2040static struct clk i2c1_ick = { 2021static struct clk i2c1_ick = {
2041 .name = "i2c_ick", 2022 .name = "i2c1_ick",
2042 .ops = &clkops_omap2_dflt_wait, 2023 .ops = &clkops_omap2_dflt_wait,
2043 .id = 1,
2044 .parent = &core_l4_ick, 2024 .parent = &core_l4_ick,
2045 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2025 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2046 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 2026 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
@@ -2089,9 +2069,8 @@ static struct clk gpt10_ick = {
2089}; 2069};
2090 2070
2091static struct clk mcbsp5_ick = { 2071static struct clk mcbsp5_ick = {
2092 .name = "mcbsp_ick", 2072 .name = "mcbsp5_ick",
2093 .ops = &clkops_omap2_dflt_wait, 2073 .ops = &clkops_omap2_dflt_wait,
2094 .id = 5,
2095 .parent = &core_l4_ick, 2074 .parent = &core_l4_ick,
2096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2075 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2097 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 2076 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -2100,9 +2079,8 @@ static struct clk mcbsp5_ick = {
2100}; 2079};
2101 2080
2102static struct clk mcbsp1_ick = { 2081static struct clk mcbsp1_ick = {
2103 .name = "mcbsp_ick", 2082 .name = "mcbsp1_ick",
2104 .ops = &clkops_omap2_dflt_wait, 2083 .ops = &clkops_omap2_dflt_wait,
2105 .id = 1,
2106 .parent = &core_l4_ick, 2084 .parent = &core_l4_ick,
2107 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2085 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2108 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 2086 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -2897,9 +2875,8 @@ static struct clk gpt2_ick = {
2897}; 2875};
2898 2876
2899static struct clk mcbsp2_ick = { 2877static struct clk mcbsp2_ick = {
2900 .name = "mcbsp_ick", 2878 .name = "mcbsp2_ick",
2901 .ops = &clkops_omap2_dflt_wait, 2879 .ops = &clkops_omap2_dflt_wait,
2902 .id = 2,
2903 .parent = &per_l4_ick, 2880 .parent = &per_l4_ick,
2904 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2881 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2905 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2882 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2908,9 +2885,8 @@ static struct clk mcbsp2_ick = {
2908}; 2885};
2909 2886
2910static struct clk mcbsp3_ick = { 2887static struct clk mcbsp3_ick = {
2911 .name = "mcbsp_ick", 2888 .name = "mcbsp3_ick",
2912 .ops = &clkops_omap2_dflt_wait, 2889 .ops = &clkops_omap2_dflt_wait,
2913 .id = 3,
2914 .parent = &per_l4_ick, 2890 .parent = &per_l4_ick,
2915 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2891 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2916 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2892 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2919,9 +2895,8 @@ static struct clk mcbsp3_ick = {
2919}; 2895};
2920 2896
2921static struct clk mcbsp4_ick = { 2897static struct clk mcbsp4_ick = {
2922 .name = "mcbsp_ick", 2898 .name = "mcbsp4_ick",
2923 .ops = &clkops_omap2_dflt_wait, 2899 .ops = &clkops_omap2_dflt_wait,
2924 .id = 4,
2925 .parent = &per_l4_ick, 2900 .parent = &per_l4_ick,
2926 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2901 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2927 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2902 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@@ -2936,9 +2911,8 @@ static const struct clksel mcbsp_234_clksel[] = {
2936}; 2911};
2937 2912
2938static struct clk mcbsp2_fck = { 2913static struct clk mcbsp2_fck = {
2939 .name = "mcbsp_fck", 2914 .name = "mcbsp2_fck",
2940 .ops = &clkops_omap2_dflt_wait, 2915 .ops = &clkops_omap2_dflt_wait,
2941 .id = 2,
2942 .init = &omap2_init_clksel_parent, 2916 .init = &omap2_init_clksel_parent,
2943 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2917 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2944 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2918 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2950,9 +2924,8 @@ static struct clk mcbsp2_fck = {
2950}; 2924};
2951 2925
2952static struct clk mcbsp3_fck = { 2926static struct clk mcbsp3_fck = {
2953 .name = "mcbsp_fck", 2927 .name = "mcbsp3_fck",
2954 .ops = &clkops_omap2_dflt_wait, 2928 .ops = &clkops_omap2_dflt_wait,
2955 .id = 3,
2956 .init = &omap2_init_clksel_parent, 2929 .init = &omap2_init_clksel_parent,
2957 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2930 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2958 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2931 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2964,9 +2937,8 @@ static struct clk mcbsp3_fck = {
2964}; 2937};
2965 2938
2966static struct clk mcbsp4_fck = { 2939static struct clk mcbsp4_fck = {
2967 .name = "mcbsp_fck", 2940 .name = "mcbsp4_fck",
2968 .ops = &clkops_omap2_dflt_wait, 2941 .ops = &clkops_omap2_dflt_wait,
2969 .id = 4,
2970 .init = &omap2_init_clksel_parent, 2942 .init = &omap2_init_clksel_parent,
2971 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2943 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2972 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2944 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,