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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-01-19 19:30:52 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-19 19:30:52 -0500
commit6468e3b18777ecfffa6738e365896be9f17403f2 (patch)
tree0c8323159c431d60b9397a594a14e375ba3da429 /arch/arm/mach-omap2/clock34xx_data.c
parent883edfdd58419b0cc298db14ba25c26d55c6d1af (diff)
OMAP3: clock: Remove unnecessarily .init initializers from OMAP3 clocks
The first thing that omap2_init_clksel_parent() does is check for a non-zero .clksel field in the struct clk. Therefore, it is pointless calling this function on clocks where the clksel field is unset. Remove init calls to omap2_init_clksel_parent() on clocks without a clksel field. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock34xx_data.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index c6031d74d6f6..74930e3158e3 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = {
671 .name = "dpll4_m3x2_ck", 671 .name = "dpll4_m3x2_ck",
672 .ops = &clkops_omap2_dflt_wait, 672 .ops = &clkops_omap2_dflt_wait,
673 .parent = &dpll4_m3_ck, 673 .parent = &dpll4_m3_ck,
674 .init = &omap2_init_clksel_parent,
675 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 674 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
676 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 675 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
677 .flags = INVERT_ENABLE, 676 .flags = INVERT_ENABLE,
@@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = {
811 .name = "dpll4_m6x2_ck", 810 .name = "dpll4_m6x2_ck",
812 .ops = &clkops_omap2_dflt_wait, 811 .ops = &clkops_omap2_dflt_wait,
813 .parent = &dpll4_m6_ck, 812 .parent = &dpll4_m6_ck,
814 .init = &omap2_init_clksel_parent,
815 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 813 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
816 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 814 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
817 .flags = INVERT_ENABLE, 815 .flags = INVERT_ENABLE,
@@ -1047,7 +1045,6 @@ static struct clk iva2_ck = {
1047 .name = "iva2_ck", 1045 .name = "iva2_ck",
1048 .ops = &clkops_omap2_dflt_wait, 1046 .ops = &clkops_omap2_dflt_wait,
1049 .parent = &dpll2_m2_ck, 1047 .parent = &dpll2_m2_ck,
1050 .init = &omap2_init_clksel_parent,
1051 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1048 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1052 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1049 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1053 .clkdm_name = "iva2_clkdm", 1050 .clkdm_name = "iva2_clkdm",
@@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = {
1121 .name = "gfx_l3_ck", 1118 .name = "gfx_l3_ck",
1122 .ops = &clkops_omap2_dflt_wait, 1119 .ops = &clkops_omap2_dflt_wait,
1123 .parent = &l3_ick, 1120 .parent = &l3_ick,
1124 .init = &omap2_init_clksel_parent,
1125 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1121 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1126 .enable_bit = OMAP_EN_GFX_SHIFT, 1122 .enable_bit = OMAP_EN_GFX_SHIFT,
1127 .recalc = &followparent_recalc, 1123 .recalc = &followparent_recalc,