ARM: OMAP: Enable GPIO debounce clock only when debounce is enabled v3

This patch changes gpio "driver" to enable debounce clock for
gpio-bank only when debounce is enabled for some gpio in that bank.

Gpio functional clocks are also renamed in clock tree, gpioX_fck ->
gpioX_dbck.

This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
domain aren't capable to generate wake-up if PER domain is in sleep
state. For this iopad wake-up should be used and needed pad
configuration should be done. Enabling iopad wake-up for gpio pads is
left for bootloader or omap mux configuration in kernel.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 18 insertions, 18 deletions

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c38a8a09692f..7217a0824ec4 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2280,8 +2280,8 @@ static struct clk wkup_32k_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio1_fck = {
-        .name           = "gpio1_fck",
+static struct clk gpio1_dbck = {
+        .name           = "gpio1_dbck",
         .parent         = &wkup_32k_fck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
@@ -2527,8 +2527,8 @@ static struct clk per_32k_alwon_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio6_fck = {
-        .name           = "gpio6_fck",
+static struct clk gpio6_dbck = {
+        .name           = "gpio6_dbck",
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
@@ -2537,8 +2537,8 @@ static struct clk gpio6_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio5_fck = {
-        .name           = "gpio5_fck",
+static struct clk gpio5_dbck = {
+        .name           = "gpio5_dbck",
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
@@ -2547,8 +2547,8 @@ static struct clk gpio5_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio4_fck = {
-        .name           = "gpio4_fck",
+static struct clk gpio4_dbck = {
+        .name           = "gpio4_dbck",
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
@@ -2557,8 +2557,8 @@ static struct clk gpio4_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio3_fck = {
-        .name           = "gpio3_fck",
+static struct clk gpio3_dbck = {
+        .name           = "gpio3_dbck",
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
@@ -2567,8 +2567,8 @@ static struct clk gpio3_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk gpio2_fck = {
-        .name           = "gpio2_fck",
+static struct clk gpio2_dbck = {
+        .name           = "gpio2_dbck",
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
@@ -3170,7 +3170,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
         &usim_fck,
         &gpt1_fck,
         &wkup_32k_fck,
-        &gpio1_fck,
+        &gpio1_dbck,
         &wdt2_fck,
         &wkup_l4_ick,
         &usim_ick,
@@ -3192,11 +3192,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
         &gpt8_fck,
         &gpt9_fck,
         &per_32k_alwon_fck,
-        &gpio6_fck,
-        &gpio5_fck,
-        &gpio4_fck,
-        &gpio3_fck,
-        &gpio2_fck,
+        &gpio6_dbck,
+        &gpio5_dbck,
+        &gpio4_dbck,
+        &gpio3_dbck,
+        &gpio2_dbck,
         &wdt3_fck,
         &per_l4_ick,
         &gpio6_ick,