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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-11-04 11:48:35 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 06:38:39 -0500
commit57137181e3136d4c7b20b4b95b9817efd38f8f07 (patch)
tree3a5986311d910db1a0f721e5e1cbe3f3d056fd66 /arch/arm/mach-omap2/clock34xx.h
parent897dcded6fb6565f4d1c22a55d21f135403db132 (diff)
[ARM] omap: kill PARENT_CONTROLS_CLOCK
PARENT_CONTROLS_CLOCK just makes enable/disable no-op, and is functionally an alias for ALWAYS_ENABLED. This can be handled in the same way, using clkops_null. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r--arch/arm/mach-omap2/clock34xx.h196
1 files changed, 100 insertions, 96 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index b56fd2897626..203e2bd3b3b0 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -295,9 +295,9 @@ static struct clk dpll1_ck = {
295 */ 295 */
296static struct clk dpll1_x2_ck = { 296static struct clk dpll1_x2_ck = {
297 .name = "dpll1_x2_ck", 297 .name = "dpll1_x2_ck",
298 .ops = &clkops_null,
298 .parent = &dpll1_ck, 299 .parent = &dpll1_ck,
299 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 300 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
300 PARENT_CONTROLS_CLOCK,
301 .recalc = &omap3_clkoutx2_recalc, 301 .recalc = &omap3_clkoutx2_recalc,
302}; 302};
303 303
@@ -313,13 +313,13 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = {
313 */ 313 */
314static struct clk dpll1_x2m2_ck = { 314static struct clk dpll1_x2m2_ck = {
315 .name = "dpll1_x2m2_ck", 315 .name = "dpll1_x2m2_ck",
316 .ops = &clkops_null,
316 .parent = &dpll1_x2_ck, 317 .parent = &dpll1_x2_ck,
317 .init = &omap2_init_clksel_parent, 318 .init = &omap2_init_clksel_parent,
318 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), 319 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
319 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, 320 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
320 .clksel = div16_dpll1_x2m2_clksel, 321 .clksel = div16_dpll1_x2m2_clksel,
321 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 322 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
322 PARENT_CONTROLS_CLOCK,
323 .recalc = &omap2_clksel_recalc, 323 .recalc = &omap2_clksel_recalc,
324}; 324};
325 325
@@ -368,14 +368,14 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = {
368 */ 368 */
369static struct clk dpll2_m2_ck = { 369static struct clk dpll2_m2_ck = {
370 .name = "dpll2_m2_ck", 370 .name = "dpll2_m2_ck",
371 .ops = &clkops_null,
371 .parent = &dpll2_ck, 372 .parent = &dpll2_ck,
372 .init = &omap2_init_clksel_parent, 373 .init = &omap2_init_clksel_parent,
373 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, 374 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
374 OMAP3430_CM_CLKSEL2_PLL), 375 OMAP3430_CM_CLKSEL2_PLL),
375 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, 376 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
376 .clksel = div16_dpll2_m2x2_clksel, 377 .clksel = div16_dpll2_m2x2_clksel,
377 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 378 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
378 PARENT_CONTROLS_CLOCK,
379 .recalc = &omap2_clksel_recalc, 379 .recalc = &omap2_clksel_recalc,
380}; 380};
381 381
@@ -416,9 +416,9 @@ static struct clk dpll3_ck = {
416 */ 416 */
417static struct clk dpll3_x2_ck = { 417static struct clk dpll3_x2_ck = {
418 .name = "dpll3_x2_ck", 418 .name = "dpll3_x2_ck",
419 .ops = &clkops_null,
419 .parent = &dpll3_ck, 420 .parent = &dpll3_ck,
420 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 421 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
421 PARENT_CONTROLS_CLOCK,
422 .recalc = &omap3_clkoutx2_recalc, 422 .recalc = &omap3_clkoutx2_recalc,
423}; 423};
424 424
@@ -469,13 +469,13 @@ static const struct clksel div31_dpll3m2_clksel[] = {
469 */ 469 */
470static struct clk dpll3_m2_ck = { 470static struct clk dpll3_m2_ck = {
471 .name = "dpll3_m2_ck", 471 .name = "dpll3_m2_ck",
472 .ops = &clkops_null,
472 .parent = &dpll3_ck, 473 .parent = &dpll3_ck,
473 .init = &omap2_init_clksel_parent, 474 .init = &omap2_init_clksel_parent,
474 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 475 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
475 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, 476 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
476 .clksel = div31_dpll3m2_clksel, 477 .clksel = div31_dpll3m2_clksel,
477 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 478 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
478 PARENT_CONTROLS_CLOCK,
479 .recalc = &omap2_clksel_recalc, 479 .recalc = &omap2_clksel_recalc,
480}; 480};
481 481
@@ -487,12 +487,12 @@ static const struct clksel core_ck_clksel[] = {
487 487
488static struct clk core_ck = { 488static struct clk core_ck = {
489 .name = "core_ck", 489 .name = "core_ck",
490 .ops = &clkops_null,
490 .init = &omap2_init_clksel_parent, 491 .init = &omap2_init_clksel_parent,
491 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 492 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
492 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 493 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
493 .clksel = core_ck_clksel, 494 .clksel = core_ck_clksel,
494 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 495 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
495 PARENT_CONTROLS_CLOCK,
496 .recalc = &omap2_clksel_recalc, 496 .recalc = &omap2_clksel_recalc,
497}; 497};
498 498
@@ -504,12 +504,12 @@ static const struct clksel dpll3_m2x2_ck_clksel[] = {
504 504
505static struct clk dpll3_m2x2_ck = { 505static struct clk dpll3_m2x2_ck = {
506 .name = "dpll3_m2x2_ck", 506 .name = "dpll3_m2x2_ck",
507 .ops = &clkops_null,
507 .init = &omap2_init_clksel_parent, 508 .init = &omap2_init_clksel_parent,
508 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 509 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
509 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 510 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
510 .clksel = dpll3_m2x2_ck_clksel, 511 .clksel = dpll3_m2x2_ck_clksel,
511 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 512 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
512 PARENT_CONTROLS_CLOCK,
513 .recalc = &omap2_clksel_recalc, 513 .recalc = &omap2_clksel_recalc,
514}; 514};
515 515
@@ -522,13 +522,13 @@ static const struct clksel div16_dpll3_clksel[] = {
522/* This virtual clock is the source for dpll3_m3x2_ck */ 522/* This virtual clock is the source for dpll3_m3x2_ck */
523static struct clk dpll3_m3_ck = { 523static struct clk dpll3_m3_ck = {
524 .name = "dpll3_m3_ck", 524 .name = "dpll3_m3_ck",
525 .ops = &clkops_null,
525 .parent = &dpll3_ck, 526 .parent = &dpll3_ck,
526 .init = &omap2_init_clksel_parent, 527 .init = &omap2_init_clksel_parent,
527 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 528 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
528 .clksel_mask = OMAP3430_DIV_DPLL3_MASK, 529 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
529 .clksel = div16_dpll3_clksel, 530 .clksel = div16_dpll3_clksel,
530 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 531 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
531 PARENT_CONTROLS_CLOCK,
532 .recalc = &omap2_clksel_recalc, 532 .recalc = &omap2_clksel_recalc,
533}; 533};
534 534
@@ -550,13 +550,13 @@ static const struct clksel emu_core_alwon_ck_clksel[] = {
550 550
551static struct clk emu_core_alwon_ck = { 551static struct clk emu_core_alwon_ck = {
552 .name = "emu_core_alwon_ck", 552 .name = "emu_core_alwon_ck",
553 .ops = &clkops_null,
553 .parent = &dpll3_m3x2_ck, 554 .parent = &dpll3_m3x2_ck,
554 .init = &omap2_init_clksel_parent, 555 .init = &omap2_init_clksel_parent,
555 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 556 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
556 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 557 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
557 .clksel = emu_core_alwon_ck_clksel, 558 .clksel = emu_core_alwon_ck_clksel,
558 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 559 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
559 PARENT_CONTROLS_CLOCK,
560 .recalc = &omap2_clksel_recalc, 560 .recalc = &omap2_clksel_recalc,
561}; 561};
562 562
@@ -599,9 +599,9 @@ static struct clk dpll4_ck = {
599 */ 599 */
600static struct clk dpll4_x2_ck = { 600static struct clk dpll4_x2_ck = {
601 .name = "dpll4_x2_ck", 601 .name = "dpll4_x2_ck",
602 .ops = &clkops_null,
602 .parent = &dpll4_ck, 603 .parent = &dpll4_ck,
603 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 604 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
604 PARENT_CONTROLS_CLOCK,
605 .recalc = &omap3_clkoutx2_recalc, 605 .recalc = &omap3_clkoutx2_recalc,
606}; 606};
607 607
@@ -613,13 +613,13 @@ static const struct clksel div16_dpll4_clksel[] = {
613/* This virtual clock is the source for dpll4_m2x2_ck */ 613/* This virtual clock is the source for dpll4_m2x2_ck */
614static struct clk dpll4_m2_ck = { 614static struct clk dpll4_m2_ck = {
615 .name = "dpll4_m2_ck", 615 .name = "dpll4_m2_ck",
616 .ops = &clkops_null,
616 .parent = &dpll4_ck, 617 .parent = &dpll4_ck,
617 .init = &omap2_init_clksel_parent, 618 .init = &omap2_init_clksel_parent,
618 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), 619 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
619 .clksel_mask = OMAP3430_DIV_96M_MASK, 620 .clksel_mask = OMAP3430_DIV_96M_MASK,
620 .clksel = div16_dpll4_clksel, 621 .clksel = div16_dpll4_clksel,
621 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 622 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
622 PARENT_CONTROLS_CLOCK,
623 .recalc = &omap2_clksel_recalc, 623 .recalc = &omap2_clksel_recalc,
624}; 624};
625 625
@@ -641,21 +641,21 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = {
641 641
642static struct clk omap_96m_alwon_fck = { 642static struct clk omap_96m_alwon_fck = {
643 .name = "omap_96m_alwon_fck", 643 .name = "omap_96m_alwon_fck",
644 .ops = &clkops_null,
644 .parent = &dpll4_m2x2_ck, 645 .parent = &dpll4_m2x2_ck,
645 .init = &omap2_init_clksel_parent, 646 .init = &omap2_init_clksel_parent,
646 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 647 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
647 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 648 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
648 .clksel = omap_96m_alwon_fck_clksel, 649 .clksel = omap_96m_alwon_fck_clksel,
649 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 650 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
650 PARENT_CONTROLS_CLOCK,
651 .recalc = &omap2_clksel_recalc, 651 .recalc = &omap2_clksel_recalc,
652}; 652};
653 653
654static struct clk omap_96m_fck = { 654static struct clk omap_96m_fck = {
655 .name = "omap_96m_fck", 655 .name = "omap_96m_fck",
656 .ops = &clkops_null,
656 .parent = &omap_96m_alwon_fck, 657 .parent = &omap_96m_alwon_fck,
657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 658 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
658 PARENT_CONTROLS_CLOCK,
659 .recalc = &followparent_recalc, 659 .recalc = &followparent_recalc,
660}; 660};
661 661
@@ -667,26 +667,26 @@ static const struct clksel cm_96m_fck_clksel[] = {
667 667
668static struct clk cm_96m_fck = { 668static struct clk cm_96m_fck = {
669 .name = "cm_96m_fck", 669 .name = "cm_96m_fck",
670 .ops = &clkops_null,
670 .parent = &dpll4_m2x2_ck, 671 .parent = &dpll4_m2x2_ck,
671 .init = &omap2_init_clksel_parent, 672 .init = &omap2_init_clksel_parent,
672 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 673 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
673 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 674 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
674 .clksel = cm_96m_fck_clksel, 675 .clksel = cm_96m_fck_clksel,
675 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 676 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
676 PARENT_CONTROLS_CLOCK,
677 .recalc = &omap2_clksel_recalc, 677 .recalc = &omap2_clksel_recalc,
678}; 678};
679 679
680/* This virtual clock is the source for dpll4_m3x2_ck */ 680/* This virtual clock is the source for dpll4_m3x2_ck */
681static struct clk dpll4_m3_ck = { 681static struct clk dpll4_m3_ck = {
682 .name = "dpll4_m3_ck", 682 .name = "dpll4_m3_ck",
683 .ops = &clkops_null,
683 .parent = &dpll4_ck, 684 .parent = &dpll4_ck,
684 .init = &omap2_init_clksel_parent, 685 .init = &omap2_init_clksel_parent,
685 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 686 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
686 .clksel_mask = OMAP3430_CLKSEL_TV_MASK, 687 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
687 .clksel = div16_dpll4_clksel, 688 .clksel = div16_dpll4_clksel,
688 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 689 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
689 PARENT_CONTROLS_CLOCK,
690 .recalc = &omap2_clksel_recalc, 690 .recalc = &omap2_clksel_recalc,
691}; 691};
692 692
@@ -709,13 +709,13 @@ static const struct clksel virt_omap_54m_fck_clksel[] = {
709 709
710static struct clk virt_omap_54m_fck = { 710static struct clk virt_omap_54m_fck = {
711 .name = "virt_omap_54m_fck", 711 .name = "virt_omap_54m_fck",
712 .ops = &clkops_null,
712 .parent = &dpll4_m3x2_ck, 713 .parent = &dpll4_m3x2_ck,
713 .init = &omap2_init_clksel_parent, 714 .init = &omap2_init_clksel_parent,
714 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 715 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
715 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 716 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
716 .clksel = virt_omap_54m_fck_clksel, 717 .clksel = virt_omap_54m_fck_clksel,
717 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 718 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
718 PARENT_CONTROLS_CLOCK,
719 .recalc = &omap2_clksel_recalc, 719 .recalc = &omap2_clksel_recalc,
720}; 720};
721 721
@@ -737,12 +737,12 @@ static const struct clksel omap_54m_clksel[] = {
737 737
738static struct clk omap_54m_fck = { 738static struct clk omap_54m_fck = {
739 .name = "omap_54m_fck", 739 .name = "omap_54m_fck",
740 .ops = &clkops_null,
740 .init = &omap2_init_clksel_parent, 741 .init = &omap2_init_clksel_parent,
741 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 742 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
742 .clksel_mask = OMAP3430_SOURCE_54M, 743 .clksel_mask = OMAP3430_SOURCE_54M,
743 .clksel = omap_54m_clksel, 744 .clksel = omap_54m_clksel,
744 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 745 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
745 PARENT_CONTROLS_CLOCK,
746 .recalc = &omap2_clksel_recalc, 746 .recalc = &omap2_clksel_recalc,
747}; 747};
748 748
@@ -764,34 +764,34 @@ static const struct clksel omap_48m_clksel[] = {
764 764
765static struct clk omap_48m_fck = { 765static struct clk omap_48m_fck = {
766 .name = "omap_48m_fck", 766 .name = "omap_48m_fck",
767 .ops = &clkops_null,
767 .init = &omap2_init_clksel_parent, 768 .init = &omap2_init_clksel_parent,
768 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 769 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
769 .clksel_mask = OMAP3430_SOURCE_48M, 770 .clksel_mask = OMAP3430_SOURCE_48M,
770 .clksel = omap_48m_clksel, 771 .clksel = omap_48m_clksel,
771 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 772 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
772 PARENT_CONTROLS_CLOCK,
773 .recalc = &omap2_clksel_recalc, 773 .recalc = &omap2_clksel_recalc,
774}; 774};
775 775
776static struct clk omap_12m_fck = { 776static struct clk omap_12m_fck = {
777 .name = "omap_12m_fck", 777 .name = "omap_12m_fck",
778 .ops = &clkops_null,
778 .parent = &omap_48m_fck, 779 .parent = &omap_48m_fck,
779 .fixed_div = 4, 780 .fixed_div = 4,
780 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 781 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
781 PARENT_CONTROLS_CLOCK,
782 .recalc = &omap2_fixed_divisor_recalc, 782 .recalc = &omap2_fixed_divisor_recalc,
783}; 783};
784 784
785/* This virstual clock is the source for dpll4_m4x2_ck */ 785/* This virstual clock is the source for dpll4_m4x2_ck */
786static struct clk dpll4_m4_ck = { 786static struct clk dpll4_m4_ck = {
787 .name = "dpll4_m4_ck", 787 .name = "dpll4_m4_ck",
788 .ops = &clkops_null,
788 .parent = &dpll4_ck, 789 .parent = &dpll4_ck,
789 .init = &omap2_init_clksel_parent, 790 .init = &omap2_init_clksel_parent,
790 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 791 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
791 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, 792 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
792 .clksel = div16_dpll4_clksel, 793 .clksel = div16_dpll4_clksel,
793 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 794 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
794 PARENT_CONTROLS_CLOCK,
795 .recalc = &omap2_clksel_recalc, 795 .recalc = &omap2_clksel_recalc,
796}; 796};
797 797
@@ -808,13 +808,13 @@ static struct clk dpll4_m4x2_ck = {
808/* This virtual clock is the source for dpll4_m5x2_ck */ 808/* This virtual clock is the source for dpll4_m5x2_ck */
809static struct clk dpll4_m5_ck = { 809static struct clk dpll4_m5_ck = {
810 .name = "dpll4_m5_ck", 810 .name = "dpll4_m5_ck",
811 .ops = &clkops_null,
811 .parent = &dpll4_ck, 812 .parent = &dpll4_ck,
812 .init = &omap2_init_clksel_parent, 813 .init = &omap2_init_clksel_parent,
813 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 814 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
814 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 815 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
815 .clksel = div16_dpll4_clksel, 816 .clksel = div16_dpll4_clksel,
816 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 817 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
817 PARENT_CONTROLS_CLOCK,
818 .recalc = &omap2_clksel_recalc, 818 .recalc = &omap2_clksel_recalc,
819}; 819};
820 820
@@ -831,13 +831,13 @@ static struct clk dpll4_m5x2_ck = {
831/* This virtual clock is the source for dpll4_m6x2_ck */ 831/* This virtual clock is the source for dpll4_m6x2_ck */
832static struct clk dpll4_m6_ck = { 832static struct clk dpll4_m6_ck = {
833 .name = "dpll4_m6_ck", 833 .name = "dpll4_m6_ck",
834 .ops = &clkops_null,
834 .parent = &dpll4_ck, 835 .parent = &dpll4_ck,
835 .init = &omap2_init_clksel_parent, 836 .init = &omap2_init_clksel_parent,
836 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 837 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
837 .clksel_mask = OMAP3430_DIV_DPLL4_MASK, 838 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
838 .clksel = div16_dpll4_clksel, 839 .clksel = div16_dpll4_clksel,
839 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 840 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
840 PARENT_CONTROLS_CLOCK,
841 .recalc = &omap2_clksel_recalc, 841 .recalc = &omap2_clksel_recalc,
842}; 842};
843 843
@@ -854,9 +854,9 @@ static struct clk dpll4_m6x2_ck = {
854 854
855static struct clk emu_per_alwon_ck = { 855static struct clk emu_per_alwon_ck = {
856 .name = "emu_per_alwon_ck", 856 .name = "emu_per_alwon_ck",
857 .ops = &clkops_null,
857 .parent = &dpll4_m6x2_ck, 858 .parent = &dpll4_m6x2_ck,
858 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 859 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
859 PARENT_CONTROLS_CLOCK,
860 .recalc = &followparent_recalc, 860 .recalc = &followparent_recalc,
861}; 861};
862 862
@@ -900,13 +900,13 @@ static const struct clksel div16_dpll5_clksel[] = {
900 900
901static struct clk dpll5_m2_ck = { 901static struct clk dpll5_m2_ck = {
902 .name = "dpll5_m2_ck", 902 .name = "dpll5_m2_ck",
903 .ops = &clkops_null,
903 .parent = &dpll5_ck, 904 .parent = &dpll5_ck,
904 .init = &omap2_init_clksel_parent, 905 .init = &omap2_init_clksel_parent,
905 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 906 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
906 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 907 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
907 .clksel = div16_dpll5_clksel, 908 .clksel = div16_dpll5_clksel,
908 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 909 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
909 PARENT_CONTROLS_CLOCK,
910 .recalc = &omap2_clksel_recalc, 910 .recalc = &omap2_clksel_recalc,
911}; 911};
912 912
@@ -918,13 +918,13 @@ static const struct clksel omap_120m_fck_clksel[] = {
918 918
919static struct clk omap_120m_fck = { 919static struct clk omap_120m_fck = {
920 .name = "omap_120m_fck", 920 .name = "omap_120m_fck",
921 .ops = &clkops_null,
921 .parent = &dpll5_m2_ck, 922 .parent = &dpll5_m2_ck,
922 .init = &omap2_init_clksel_parent, 923 .init = &omap2_init_clksel_parent,
923 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 924 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
924 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, 925 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
925 .clksel = omap_120m_fck_clksel, 926 .clksel = omap_120m_fck_clksel,
926 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 927 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
927 PARENT_CONTROLS_CLOCK,
928 .recalc = &omap2_clksel_recalc, 928 .recalc = &omap2_clksel_recalc,
929}; 929};
930 930
@@ -986,11 +986,12 @@ static const struct clksel sys_clkout2_clksel[] = {
986 986
987static struct clk sys_clkout2 = { 987static struct clk sys_clkout2 = {
988 .name = "sys_clkout2", 988 .name = "sys_clkout2",
989 .ops = &clkops_null,
989 .init = &omap2_init_clksel_parent, 990 .init = &omap2_init_clksel_parent,
990 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 991 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
991 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, 992 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
992 .clksel = sys_clkout2_clksel, 993 .clksel = sys_clkout2_clksel,
993 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, 994 .flags = CLOCK_IN_OMAP343X,
994 .recalc = &omap2_clksel_recalc, 995 .recalc = &omap2_clksel_recalc,
995}; 996};
996 997
@@ -998,9 +999,9 @@ static struct clk sys_clkout2 = {
998 999
999static struct clk corex2_fck = { 1000static struct clk corex2_fck = {
1000 .name = "corex2_fck", 1001 .name = "corex2_fck",
1002 .ops = &clkops_null,
1001 .parent = &dpll3_m2x2_ck, 1003 .parent = &dpll3_m2x2_ck,
1002 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1004 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1003 PARENT_CONTROLS_CLOCK,
1004 .recalc = &followparent_recalc, 1005 .recalc = &followparent_recalc,
1005}; 1006};
1006 1007
@@ -1017,13 +1018,13 @@ static const struct clksel div2_core_clksel[] = {
1017 */ 1018 */
1018static struct clk dpll1_fck = { 1019static struct clk dpll1_fck = {
1019 .name = "dpll1_fck", 1020 .name = "dpll1_fck",
1021 .ops = &clkops_null,
1020 .parent = &core_ck, 1022 .parent = &core_ck,
1021 .init = &omap2_init_clksel_parent, 1023 .init = &omap2_init_clksel_parent,
1022 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 1024 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1023 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, 1025 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1024 .clksel = div2_core_clksel, 1026 .clksel = div2_core_clksel,
1025 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1027 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1026 PARENT_CONTROLS_CLOCK,
1027 .recalc = &omap2_clksel_recalc, 1028 .recalc = &omap2_clksel_recalc,
1028}; 1029};
1029 1030
@@ -1041,13 +1042,13 @@ static const struct clksel mpu_clksel[] = {
1041 1042
1042static struct clk mpu_ck = { 1043static struct clk mpu_ck = {
1043 .name = "mpu_ck", 1044 .name = "mpu_ck",
1045 .ops = &clkops_null,
1044 .parent = &dpll1_x2m2_ck, 1046 .parent = &dpll1_x2m2_ck,
1045 .init = &omap2_init_clksel_parent, 1047 .init = &omap2_init_clksel_parent,
1046 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1048 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1049 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1048 .clksel = mpu_clksel, 1050 .clksel = mpu_clksel,
1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1051 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1050 PARENT_CONTROLS_CLOCK,
1051 .clkdm_name = "mpu_clkdm", 1052 .clkdm_name = "mpu_clkdm",
1052 .recalc = &omap2_clksel_recalc, 1053 .recalc = &omap2_clksel_recalc,
1053}; 1054};
@@ -1066,13 +1067,13 @@ static const struct clksel arm_fck_clksel[] = {
1066 1067
1067static struct clk arm_fck = { 1068static struct clk arm_fck = {
1068 .name = "arm_fck", 1069 .name = "arm_fck",
1070 .ops = &clkops_null,
1069 .parent = &mpu_ck, 1071 .parent = &mpu_ck,
1070 .init = &omap2_init_clksel_parent, 1072 .init = &omap2_init_clksel_parent,
1071 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1073 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1074 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1073 .clksel = arm_fck_clksel, 1075 .clksel = arm_fck_clksel,
1074 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1076 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1075 PARENT_CONTROLS_CLOCK,
1076 .recalc = &omap2_clksel_recalc, 1077 .recalc = &omap2_clksel_recalc,
1077}; 1078};
1078 1079
@@ -1084,21 +1085,21 @@ static struct clk arm_fck = {
1084 */ 1085 */
1085static struct clk emu_mpu_alwon_ck = { 1086static struct clk emu_mpu_alwon_ck = {
1086 .name = "emu_mpu_alwon_ck", 1087 .name = "emu_mpu_alwon_ck",
1088 .ops = &clkops_null,
1087 .parent = &mpu_ck, 1089 .parent = &mpu_ck,
1088 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1090 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1089 PARENT_CONTROLS_CLOCK,
1090 .recalc = &followparent_recalc, 1091 .recalc = &followparent_recalc,
1091}; 1092};
1092 1093
1093static struct clk dpll2_fck = { 1094static struct clk dpll2_fck = {
1094 .name = "dpll2_fck", 1095 .name = "dpll2_fck",
1096 .ops = &clkops_null,
1095 .parent = &core_ck, 1097 .parent = &core_ck,
1096 .init = &omap2_init_clksel_parent, 1098 .init = &omap2_init_clksel_parent,
1097 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 1099 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1098 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, 1100 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1099 .clksel = div2_core_clksel, 1101 .clksel = div2_core_clksel,
1100 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1102 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1101 PARENT_CONTROLS_CLOCK,
1102 .recalc = &omap2_clksel_recalc, 1103 .recalc = &omap2_clksel_recalc,
1103}; 1104};
1104 1105
@@ -1134,13 +1135,13 @@ static struct clk iva2_ck = {
1134 1135
1135static struct clk l3_ick = { 1136static struct clk l3_ick = {
1136 .name = "l3_ick", 1137 .name = "l3_ick",
1138 .ops = &clkops_null,
1137 .parent = &core_ck, 1139 .parent = &core_ck,
1138 .init = &omap2_init_clksel_parent, 1140 .init = &omap2_init_clksel_parent,
1139 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1141 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1140 .clksel_mask = OMAP3430_CLKSEL_L3_MASK, 1142 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1141 .clksel = div2_core_clksel, 1143 .clksel = div2_core_clksel,
1142 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1144 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1143 PARENT_CONTROLS_CLOCK,
1144 .clkdm_name = "core_l3_clkdm", 1145 .clkdm_name = "core_l3_clkdm",
1145 .recalc = &omap2_clksel_recalc, 1146 .recalc = &omap2_clksel_recalc,
1146}; 1147};
@@ -1152,13 +1153,13 @@ static const struct clksel div2_l3_clksel[] = {
1152 1153
1153static struct clk l4_ick = { 1154static struct clk l4_ick = {
1154 .name = "l4_ick", 1155 .name = "l4_ick",
1156 .ops = &clkops_null,
1155 .parent = &l3_ick, 1157 .parent = &l3_ick,
1156 .init = &omap2_init_clksel_parent, 1158 .init = &omap2_init_clksel_parent,
1157 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1159 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1158 .clksel_mask = OMAP3430_CLKSEL_L4_MASK, 1160 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1159 .clksel = div2_l3_clksel, 1161 .clksel = div2_l3_clksel,
1160 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1162 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1161 PARENT_CONTROLS_CLOCK,
1162 .clkdm_name = "core_l4_clkdm", 1163 .clkdm_name = "core_l4_clkdm",
1163 .recalc = &omap2_clksel_recalc, 1164 .recalc = &omap2_clksel_recalc,
1164 1165
@@ -1171,12 +1172,13 @@ static const struct clksel div2_l4_clksel[] = {
1171 1172
1172static struct clk rm_ick = { 1173static struct clk rm_ick = {
1173 .name = "rm_ick", 1174 .name = "rm_ick",
1175 .ops = &clkops_null,
1174 .parent = &l4_ick, 1176 .parent = &l4_ick,
1175 .init = &omap2_init_clksel_parent, 1177 .init = &omap2_init_clksel_parent,
1176 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 1178 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1177 .clksel_mask = OMAP3430_CLKSEL_RM_MASK, 1179 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1178 .clksel = div2_l4_clksel, 1180 .clksel = div2_l4_clksel,
1179 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, 1181 .flags = CLOCK_IN_OMAP343X,
1180 .recalc = &omap2_clksel_recalc, 1182 .recalc = &omap2_clksel_recalc,
1181}; 1183};
1182 1184
@@ -1202,21 +1204,22 @@ static struct clk gfx_l3_ck = {
1202 1204
1203static struct clk gfx_l3_fck = { 1205static struct clk gfx_l3_fck = {
1204 .name = "gfx_l3_fck", 1206 .name = "gfx_l3_fck",
1207 .ops = &clkops_null,
1205 .parent = &gfx_l3_ck, 1208 .parent = &gfx_l3_ck,
1206 .init = &omap2_init_clksel_parent, 1209 .init = &omap2_init_clksel_parent,
1207 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1210 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1208 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1211 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1209 .clksel = gfx_l3_clksel, 1212 .clksel = gfx_l3_clksel,
1210 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES | 1213 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1211 PARENT_CONTROLS_CLOCK,
1212 .clkdm_name = "gfx_3430es1_clkdm", 1214 .clkdm_name = "gfx_3430es1_clkdm",
1213 .recalc = &omap2_clksel_recalc, 1215 .recalc = &omap2_clksel_recalc,
1214}; 1216};
1215 1217
1216static struct clk gfx_l3_ick = { 1218static struct clk gfx_l3_ick = {
1217 .name = "gfx_l3_ick", 1219 .name = "gfx_l3_ick",
1220 .ops = &clkops_null,
1218 .parent = &gfx_l3_ck, 1221 .parent = &gfx_l3_ck,
1219 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, 1222 .flags = CLOCK_IN_OMAP3430ES1,
1220 .clkdm_name = "gfx_3430es1_clkdm", 1223 .clkdm_name = "gfx_3430es1_clkdm",
1221 .recalc = &followparent_recalc, 1224 .recalc = &followparent_recalc,
1222}; 1225};
@@ -1365,9 +1368,9 @@ static struct clk usbtll_fck = {
1365 1368
1366static struct clk core_96m_fck = { 1369static struct clk core_96m_fck = {
1367 .name = "core_96m_fck", 1370 .name = "core_96m_fck",
1371 .ops = &clkops_null,
1368 .parent = &omap_96m_fck, 1372 .parent = &omap_96m_fck,
1369 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1373 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1370 PARENT_CONTROLS_CLOCK,
1371 .clkdm_name = "core_l4_clkdm", 1374 .clkdm_name = "core_l4_clkdm",
1372 .recalc = &followparent_recalc, 1375 .recalc = &followparent_recalc,
1373}; 1376};
@@ -1499,9 +1502,9 @@ static struct clk mcbsp1_fck = {
1499 1502
1500static struct clk core_48m_fck = { 1503static struct clk core_48m_fck = {
1501 .name = "core_48m_fck", 1504 .name = "core_48m_fck",
1505 .ops = &clkops_null,
1502 .parent = &omap_48m_fck, 1506 .parent = &omap_48m_fck,
1503 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1507 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1504 PARENT_CONTROLS_CLOCK,
1505 .clkdm_name = "core_l4_clkdm", 1508 .clkdm_name = "core_l4_clkdm",
1506 .recalc = &followparent_recalc, 1509 .recalc = &followparent_recalc,
1507}; 1510};
@@ -1577,9 +1580,9 @@ static struct clk fshostusb_fck = {
1577 1580
1578static struct clk core_12m_fck = { 1581static struct clk core_12m_fck = {
1579 .name = "core_12m_fck", 1582 .name = "core_12m_fck",
1583 .ops = &clkops_null,
1580 .parent = &omap_12m_fck, 1584 .parent = &omap_12m_fck,
1581 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1585 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1582 PARENT_CONTROLS_CLOCK,
1583 .clkdm_name = "core_l4_clkdm", 1586 .clkdm_name = "core_l4_clkdm",
1584 .recalc = &followparent_recalc, 1587 .recalc = &followparent_recalc,
1585}; 1588};
@@ -1625,9 +1628,10 @@ static struct clk ssi_ssr_fck = {
1625 1628
1626static struct clk ssi_sst_fck = { 1629static struct clk ssi_sst_fck = {
1627 .name = "ssi_sst_fck", 1630 .name = "ssi_sst_fck",
1631 .ops = &clkops_null,
1628 .parent = &ssi_ssr_fck, 1632 .parent = &ssi_ssr_fck,
1629 .fixed_div = 2, 1633 .fixed_div = 2,
1630 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, 1634 .flags = CLOCK_IN_OMAP343X,
1631 .recalc = &omap2_fixed_divisor_recalc, 1635 .recalc = &omap2_fixed_divisor_recalc,
1632}; 1636};
1633 1637
@@ -1641,10 +1645,10 @@ static struct clk ssi_sst_fck = {
1641 */ 1645 */
1642static struct clk core_l3_ick = { 1646static struct clk core_l3_ick = {
1643 .name = "core_l3_ick", 1647 .name = "core_l3_ick",
1648 .ops = &clkops_null,
1644 .parent = &l3_ick, 1649 .parent = &l3_ick,
1645 .init = &omap2_init_clk_clkdm, 1650 .init = &omap2_init_clk_clkdm,
1646 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1651 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1647 PARENT_CONTROLS_CLOCK,
1648 .clkdm_name = "core_l3_clkdm", 1652 .clkdm_name = "core_l3_clkdm",
1649 .recalc = &followparent_recalc, 1653 .recalc = &followparent_recalc,
1650}; 1654};
@@ -1671,9 +1675,9 @@ static struct clk sdrc_ick = {
1671 1675
1672static struct clk gpmc_fck = { 1676static struct clk gpmc_fck = {
1673 .name = "gpmc_fck", 1677 .name = "gpmc_fck",
1678 .ops = &clkops_null,
1674 .parent = &core_l3_ick, 1679 .parent = &core_l3_ick,
1675 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | 1680 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, /* huh? */
1676 ENABLE_ON_INIT,
1677 .clkdm_name = "core_l3_clkdm", 1681 .clkdm_name = "core_l3_clkdm",
1678 .recalc = &followparent_recalc, 1682 .recalc = &followparent_recalc,
1679}; 1683};
@@ -1682,9 +1686,9 @@ static struct clk gpmc_fck = {
1682 1686
1683static struct clk security_l3_ick = { 1687static struct clk security_l3_ick = {
1684 .name = "security_l3_ick", 1688 .name = "security_l3_ick",
1689 .ops = &clkops_null,
1685 .parent = &l3_ick, 1690 .parent = &l3_ick,
1686 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1691 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1687 PARENT_CONTROLS_CLOCK,
1688 .recalc = &followparent_recalc, 1692 .recalc = &followparent_recalc,
1689}; 1693};
1690 1694
@@ -1701,10 +1705,10 @@ static struct clk pka_ick = {
1701 1705
1702static struct clk core_l4_ick = { 1706static struct clk core_l4_ick = {
1703 .name = "core_l4_ick", 1707 .name = "core_l4_ick",
1708 .ops = &clkops_null,
1704 .parent = &l4_ick, 1709 .parent = &l4_ick,
1705 .init = &omap2_init_clk_clkdm, 1710 .init = &omap2_init_clk_clkdm,
1706 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1711 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1707 PARENT_CONTROLS_CLOCK,
1708 .clkdm_name = "core_l4_clkdm", 1712 .clkdm_name = "core_l4_clkdm",
1709 .recalc = &followparent_recalc, 1713 .recalc = &followparent_recalc,
1710}; 1714};
@@ -1984,9 +1988,9 @@ static struct clk omapctrl_ick = {
1984 1988
1985static struct clk ssi_l4_ick = { 1989static struct clk ssi_l4_ick = {
1986 .name = "ssi_l4_ick", 1990 .name = "ssi_l4_ick",
1991 .ops = &clkops_null,
1987 .parent = &l4_ick, 1992 .parent = &l4_ick,
1988 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1993 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1989 PARENT_CONTROLS_CLOCK,
1990 .clkdm_name = "core_l4_clkdm", 1994 .clkdm_name = "core_l4_clkdm",
1991 .recalc = &followparent_recalc, 1995 .recalc = &followparent_recalc,
1992}; 1996};
@@ -2028,9 +2032,9 @@ static struct clk usb_l4_ick = {
2028 2032
2029static struct clk security_l4_ick2 = { 2033static struct clk security_l4_ick2 = {
2030 .name = "security_l4_ick2", 2034 .name = "security_l4_ick2",
2035 .ops = &clkops_null,
2031 .parent = &l4_ick, 2036 .parent = &l4_ick,
2032 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2037 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2033 PARENT_CONTROLS_CLOCK,
2034 .recalc = &followparent_recalc, 2038 .recalc = &followparent_recalc,
2035}; 2039};
2036 2040
@@ -2387,20 +2391,20 @@ static struct clk gpt1_ick = {
2387 2391
2388static struct clk per_96m_fck = { 2392static struct clk per_96m_fck = {
2389 .name = "per_96m_fck", 2393 .name = "per_96m_fck",
2394 .ops = &clkops_null,
2390 .parent = &omap_96m_alwon_fck, 2395 .parent = &omap_96m_alwon_fck,
2391 .init = &omap2_init_clk_clkdm, 2396 .init = &omap2_init_clk_clkdm,
2392 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2397 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2393 PARENT_CONTROLS_CLOCK,
2394 .clkdm_name = "per_clkdm", 2398 .clkdm_name = "per_clkdm",
2395 .recalc = &followparent_recalc, 2399 .recalc = &followparent_recalc,
2396}; 2400};
2397 2401
2398static struct clk per_48m_fck = { 2402static struct clk per_48m_fck = {
2399 .name = "per_48m_fck", 2403 .name = "per_48m_fck",
2404 .ops = &clkops_null,
2400 .parent = &omap_48m_fck, 2405 .parent = &omap_48m_fck,
2401 .init = &omap2_init_clk_clkdm, 2406 .init = &omap2_init_clk_clkdm,
2402 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2407 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2403 PARENT_CONTROLS_CLOCK,
2404 .clkdm_name = "per_clkdm", 2408 .clkdm_name = "per_clkdm",
2405 .recalc = &followparent_recalc, 2409 .recalc = &followparent_recalc,
2406}; 2410};
@@ -2590,9 +2594,9 @@ static struct clk wdt3_fck = {
2590 2594
2591static struct clk per_l4_ick = { 2595static struct clk per_l4_ick = {
2592 .name = "per_l4_ick", 2596 .name = "per_l4_ick",
2597 .ops = &clkops_null,
2593 .parent = &l4_ick, 2598 .parent = &l4_ick,
2594 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2599 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2595 PARENT_CONTROLS_CLOCK,
2596 .clkdm_name = "per_clkdm", 2600 .clkdm_name = "per_clkdm",
2597 .recalc = &followparent_recalc, 2601 .recalc = &followparent_recalc,
2598}; 2602};