[ARM] OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding

The DPLL FREQSEL jitter correction bits are set based on a table in
the 34xx TRM, Table 4-38, according to the DPLL's internal clock
frequency "Fint."  Several Fint frequency ranges are missing from this
table.  Previously, we allowed these Fint frequency ranges to be
selected in the rate rounding code, but did not change the FREQSEL bits.
Correspondence with the OMAP hardware team indicates that Fint values
not in the table should not be used.  So, prevent them from being
selected during DPLL rate rounding.  This removes warnings and also
can prevent the chip from locking up.

The first pass through the rate rounding code will update the DPLL max
and min dividers appropriately, so later rate rounding passes will run
faster than the first.

Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several
test cycles of this patch - thanks Peter.

linux-omap source commit is f9c1b82f55b60fc39eaa6e7aa1fbe380c0ffe2e9.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Peter de Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 7ee131202625..aadd296c05a2 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -268,6 +268,7 @@ static struct dpll_data dpll1_dd = {
         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -341,6 +342,7 @@ static struct dpll_data dpll2_dd = {
         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -400,6 +402,7 @@ static struct dpll_data dpll3_dd = {
         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -591,6 +594,7 @@ static struct dpll_data dpll4_dd = {
         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -930,6 +934,7 @@ static struct dpll_data dpll5_dd = {
         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };