diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-11-04 11:35:03 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 06:38:39 -0500 |
commit | 897dcded6fb6565f4d1c22a55d21f135403db132 (patch) | |
tree | da9c4028ed49a1482445131760b4fc45c6524abe /arch/arm/mach-omap2/clock34xx.h | |
parent | 548d849574847b788fe846fe21a41386063be161 (diff) |
[ARM] omap: provide a NULL clock operations structure
... and use it for clocks which are ALWAYS_ENABLED. These clocks
use a non-NULL enable_reg pointer for other purposes (such as
selecting clock rates.)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.h | 85 |
1 files changed, 51 insertions, 34 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 8b188fb9beab..b56fd2897626 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -55,66 +55,66 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk); | |||
55 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | 55 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ |
56 | static struct clk omap_32k_fck = { | 56 | static struct clk omap_32k_fck = { |
57 | .name = "omap_32k_fck", | 57 | .name = "omap_32k_fck", |
58 | .ops = &clkops_null, | ||
58 | .rate = 32768, | 59 | .rate = 32768, |
59 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 60 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
60 | ALWAYS_ENABLED, | ||
61 | .recalc = &propagate_rate, | 61 | .recalc = &propagate_rate, |
62 | }; | 62 | }; |
63 | 63 | ||
64 | static struct clk secure_32k_fck = { | 64 | static struct clk secure_32k_fck = { |
65 | .name = "secure_32k_fck", | 65 | .name = "secure_32k_fck", |
66 | .ops = &clkops_null, | ||
66 | .rate = 32768, | 67 | .rate = 32768, |
67 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 68 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
68 | ALWAYS_ENABLED, | ||
69 | .recalc = &propagate_rate, | 69 | .recalc = &propagate_rate, |
70 | }; | 70 | }; |
71 | 71 | ||
72 | /* Virtual source clocks for osc_sys_ck */ | 72 | /* Virtual source clocks for osc_sys_ck */ |
73 | static struct clk virt_12m_ck = { | 73 | static struct clk virt_12m_ck = { |
74 | .name = "virt_12m_ck", | 74 | .name = "virt_12m_ck", |
75 | .ops = &clkops_null, | ||
75 | .rate = 12000000, | 76 | .rate = 12000000, |
76 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 77 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
77 | ALWAYS_ENABLED, | ||
78 | .recalc = &propagate_rate, | 78 | .recalc = &propagate_rate, |
79 | }; | 79 | }; |
80 | 80 | ||
81 | static struct clk virt_13m_ck = { | 81 | static struct clk virt_13m_ck = { |
82 | .name = "virt_13m_ck", | 82 | .name = "virt_13m_ck", |
83 | .ops = &clkops_null, | ||
83 | .rate = 13000000, | 84 | .rate = 13000000, |
84 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 85 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
85 | ALWAYS_ENABLED, | ||
86 | .recalc = &propagate_rate, | 86 | .recalc = &propagate_rate, |
87 | }; | 87 | }; |
88 | 88 | ||
89 | static struct clk virt_16_8m_ck = { | 89 | static struct clk virt_16_8m_ck = { |
90 | .name = "virt_16_8m_ck", | 90 | .name = "virt_16_8m_ck", |
91 | .ops = &clkops_null, | ||
91 | .rate = 16800000, | 92 | .rate = 16800000, |
92 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | | 93 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES, |
93 | ALWAYS_ENABLED, | ||
94 | .recalc = &propagate_rate, | 94 | .recalc = &propagate_rate, |
95 | }; | 95 | }; |
96 | 96 | ||
97 | static struct clk virt_19_2m_ck = { | 97 | static struct clk virt_19_2m_ck = { |
98 | .name = "virt_19_2m_ck", | 98 | .name = "virt_19_2m_ck", |
99 | .ops = &clkops_null, | ||
99 | .rate = 19200000, | 100 | .rate = 19200000, |
100 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 101 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
101 | ALWAYS_ENABLED, | ||
102 | .recalc = &propagate_rate, | 102 | .recalc = &propagate_rate, |
103 | }; | 103 | }; |
104 | 104 | ||
105 | static struct clk virt_26m_ck = { | 105 | static struct clk virt_26m_ck = { |
106 | .name = "virt_26m_ck", | 106 | .name = "virt_26m_ck", |
107 | .ops = &clkops_null, | ||
107 | .rate = 26000000, | 108 | .rate = 26000000, |
108 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 109 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
109 | ALWAYS_ENABLED, | ||
110 | .recalc = &propagate_rate, | 110 | .recalc = &propagate_rate, |
111 | }; | 111 | }; |
112 | 112 | ||
113 | static struct clk virt_38_4m_ck = { | 113 | static struct clk virt_38_4m_ck = { |
114 | .name = "virt_38_4m_ck", | 114 | .name = "virt_38_4m_ck", |
115 | .ops = &clkops_null, | ||
115 | .rate = 38400000, | 116 | .rate = 38400000, |
116 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 117 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
117 | ALWAYS_ENABLED, | ||
118 | .recalc = &propagate_rate, | 118 | .recalc = &propagate_rate, |
119 | }; | 119 | }; |
120 | 120 | ||
@@ -162,13 +162,13 @@ static const struct clksel osc_sys_clksel[] = { | |||
162 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | 162 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ |
163 | static struct clk osc_sys_ck = { | 163 | static struct clk osc_sys_ck = { |
164 | .name = "osc_sys_ck", | 164 | .name = "osc_sys_ck", |
165 | .ops = &clkops_null, | ||
165 | .init = &omap2_init_clksel_parent, | 166 | .init = &omap2_init_clksel_parent, |
166 | .clksel_reg = OMAP3430_PRM_CLKSEL, | 167 | .clksel_reg = OMAP3430_PRM_CLKSEL, |
167 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | 168 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
168 | .clksel = osc_sys_clksel, | 169 | .clksel = osc_sys_clksel, |
169 | /* REVISIT: deal with autoextclkmode? */ | 170 | /* REVISIT: deal with autoextclkmode? */ |
170 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 171 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, |
171 | ALWAYS_ENABLED, | ||
172 | .recalc = &omap2_clksel_recalc, | 172 | .recalc = &omap2_clksel_recalc, |
173 | }; | 173 | }; |
174 | 174 | ||
@@ -187,25 +187,28 @@ static const struct clksel sys_clksel[] = { | |||
187 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | 187 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ |
188 | static struct clk sys_ck = { | 188 | static struct clk sys_ck = { |
189 | .name = "sys_ck", | 189 | .name = "sys_ck", |
190 | .ops = &clkops_null, | ||
190 | .parent = &osc_sys_ck, | 191 | .parent = &osc_sys_ck, |
191 | .init = &omap2_init_clksel_parent, | 192 | .init = &omap2_init_clksel_parent, |
192 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | 193 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, |
193 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | 194 | .clksel_mask = OMAP_SYSCLKDIV_MASK, |
194 | .clksel = sys_clksel, | 195 | .clksel = sys_clksel, |
195 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 196 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
196 | .recalc = &omap2_clksel_recalc, | 197 | .recalc = &omap2_clksel_recalc, |
197 | }; | 198 | }; |
198 | 199 | ||
199 | static struct clk sys_altclk = { | 200 | static struct clk sys_altclk = { |
200 | .name = "sys_altclk", | 201 | .name = "sys_altclk", |
201 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 202 | .ops = &clkops_null, |
203 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
202 | .recalc = &propagate_rate, | 204 | .recalc = &propagate_rate, |
203 | }; | 205 | }; |
204 | 206 | ||
205 | /* Optional external clock input for some McBSPs */ | 207 | /* Optional external clock input for some McBSPs */ |
206 | static struct clk mcbsp_clks = { | 208 | static struct clk mcbsp_clks = { |
207 | .name = "mcbsp_clks", | 209 | .name = "mcbsp_clks", |
208 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 210 | .ops = &clkops_null, |
211 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
209 | .recalc = &propagate_rate, | 212 | .recalc = &propagate_rate, |
210 | }; | 213 | }; |
211 | 214 | ||
@@ -278,9 +281,10 @@ static struct dpll_data dpll1_dd = { | |||
278 | 281 | ||
279 | static struct clk dpll1_ck = { | 282 | static struct clk dpll1_ck = { |
280 | .name = "dpll1_ck", | 283 | .name = "dpll1_ck", |
284 | .ops = &clkops_null, | ||
281 | .parent = &sys_ck, | 285 | .parent = &sys_ck, |
282 | .dpll_data = &dpll1_dd, | 286 | .dpll_data = &dpll1_dd, |
283 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 287 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
284 | .round_rate = &omap2_dpll_round_rate, | 288 | .round_rate = &omap2_dpll_round_rate, |
285 | .recalc = &omap3_dpll_recalc, | 289 | .recalc = &omap3_dpll_recalc, |
286 | }; | 290 | }; |
@@ -398,9 +402,10 @@ static struct dpll_data dpll3_dd = { | |||
398 | 402 | ||
399 | static struct clk dpll3_ck = { | 403 | static struct clk dpll3_ck = { |
400 | .name = "dpll3_ck", | 404 | .name = "dpll3_ck", |
405 | .ops = &clkops_null, | ||
401 | .parent = &sys_ck, | 406 | .parent = &sys_ck, |
402 | .dpll_data = &dpll3_dd, | 407 | .dpll_data = &dpll3_dd, |
403 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 408 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
404 | .round_rate = &omap2_dpll_round_rate, | 409 | .round_rate = &omap2_dpll_round_rate, |
405 | .recalc = &omap3_dpll_recalc, | 410 | .recalc = &omap3_dpll_recalc, |
406 | }; | 411 | }; |
@@ -2266,9 +2271,10 @@ static struct clk gpt1_fck = { | |||
2266 | 2271 | ||
2267 | static struct clk wkup_32k_fck = { | 2272 | static struct clk wkup_32k_fck = { |
2268 | .name = "wkup_32k_fck", | 2273 | .name = "wkup_32k_fck", |
2274 | .ops = &clkops_null, | ||
2269 | .init = &omap2_init_clk_clkdm, | 2275 | .init = &omap2_init_clk_clkdm, |
2270 | .parent = &omap_32k_fck, | 2276 | .parent = &omap_32k_fck, |
2271 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2277 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
2272 | .clkdm_name = "wkup_clkdm", | 2278 | .clkdm_name = "wkup_clkdm", |
2273 | .recalc = &followparent_recalc, | 2279 | .recalc = &followparent_recalc, |
2274 | }; | 2280 | }; |
@@ -2295,8 +2301,9 @@ static struct clk wdt2_fck = { | |||
2295 | 2301 | ||
2296 | static struct clk wkup_l4_ick = { | 2302 | static struct clk wkup_l4_ick = { |
2297 | .name = "wkup_l4_ick", | 2303 | .name = "wkup_l4_ick", |
2304 | .ops = &clkops_null, | ||
2298 | .parent = &sys_ck, | 2305 | .parent = &sys_ck, |
2299 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2306 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
2300 | .clkdm_name = "wkup_clkdm", | 2307 | .clkdm_name = "wkup_clkdm", |
2301 | .recalc = &followparent_recalc, | 2308 | .recalc = &followparent_recalc, |
2302 | }; | 2309 | }; |
@@ -2514,9 +2521,10 @@ static struct clk gpt9_fck = { | |||
2514 | 2521 | ||
2515 | static struct clk per_32k_alwon_fck = { | 2522 | static struct clk per_32k_alwon_fck = { |
2516 | .name = "per_32k_alwon_fck", | 2523 | .name = "per_32k_alwon_fck", |
2524 | .ops = &clkops_null, | ||
2517 | .parent = &omap_32k_fck, | 2525 | .parent = &omap_32k_fck, |
2518 | .clkdm_name = "per_clkdm", | 2526 | .clkdm_name = "per_clkdm", |
2519 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2527 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
2520 | .recalc = &followparent_recalc, | 2528 | .recalc = &followparent_recalc, |
2521 | }; | 2529 | }; |
2522 | 2530 | ||
@@ -2859,11 +2867,12 @@ static const struct clksel emu_src_clksel[] = { | |||
2859 | */ | 2867 | */ |
2860 | static struct clk emu_src_ck = { | 2868 | static struct clk emu_src_ck = { |
2861 | .name = "emu_src_ck", | 2869 | .name = "emu_src_ck", |
2870 | .ops = &clkops_null, | ||
2862 | .init = &omap2_init_clksel_parent, | 2871 | .init = &omap2_init_clksel_parent, |
2863 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2872 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
2864 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | 2873 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, |
2865 | .clksel = emu_src_clksel, | 2874 | .clksel = emu_src_clksel, |
2866 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2875 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
2867 | .clkdm_name = "emu_clkdm", | 2876 | .clkdm_name = "emu_clkdm", |
2868 | .recalc = &omap2_clksel_recalc, | 2877 | .recalc = &omap2_clksel_recalc, |
2869 | }; | 2878 | }; |
@@ -2883,11 +2892,12 @@ static const struct clksel pclk_emu_clksel[] = { | |||
2883 | 2892 | ||
2884 | static struct clk pclk_fck = { | 2893 | static struct clk pclk_fck = { |
2885 | .name = "pclk_fck", | 2894 | .name = "pclk_fck", |
2895 | .ops = &clkops_null, | ||
2886 | .init = &omap2_init_clksel_parent, | 2896 | .init = &omap2_init_clksel_parent, |
2887 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2897 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
2888 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | 2898 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, |
2889 | .clksel = pclk_emu_clksel, | 2899 | .clksel = pclk_emu_clksel, |
2890 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2900 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
2891 | .clkdm_name = "emu_clkdm", | 2901 | .clkdm_name = "emu_clkdm", |
2892 | .recalc = &omap2_clksel_recalc, | 2902 | .recalc = &omap2_clksel_recalc, |
2893 | }; | 2903 | }; |
@@ -2906,11 +2916,12 @@ static const struct clksel pclkx2_emu_clksel[] = { | |||
2906 | 2916 | ||
2907 | static struct clk pclkx2_fck = { | 2917 | static struct clk pclkx2_fck = { |
2908 | .name = "pclkx2_fck", | 2918 | .name = "pclkx2_fck", |
2919 | .ops = &clkops_null, | ||
2909 | .init = &omap2_init_clksel_parent, | 2920 | .init = &omap2_init_clksel_parent, |
2910 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2921 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
2911 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | 2922 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, |
2912 | .clksel = pclkx2_emu_clksel, | 2923 | .clksel = pclkx2_emu_clksel, |
2913 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2924 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
2914 | .clkdm_name = "emu_clkdm", | 2925 | .clkdm_name = "emu_clkdm", |
2915 | .recalc = &omap2_clksel_recalc, | 2926 | .recalc = &omap2_clksel_recalc, |
2916 | }; | 2927 | }; |
@@ -2922,22 +2933,24 @@ static const struct clksel atclk_emu_clksel[] = { | |||
2922 | 2933 | ||
2923 | static struct clk atclk_fck = { | 2934 | static struct clk atclk_fck = { |
2924 | .name = "atclk_fck", | 2935 | .name = "atclk_fck", |
2936 | .ops = &clkops_null, | ||
2925 | .init = &omap2_init_clksel_parent, | 2937 | .init = &omap2_init_clksel_parent, |
2926 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2938 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
2927 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | 2939 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, |
2928 | .clksel = atclk_emu_clksel, | 2940 | .clksel = atclk_emu_clksel, |
2929 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2941 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
2930 | .clkdm_name = "emu_clkdm", | 2942 | .clkdm_name = "emu_clkdm", |
2931 | .recalc = &omap2_clksel_recalc, | 2943 | .recalc = &omap2_clksel_recalc, |
2932 | }; | 2944 | }; |
2933 | 2945 | ||
2934 | static struct clk traceclk_src_fck = { | 2946 | static struct clk traceclk_src_fck = { |
2935 | .name = "traceclk_src_fck", | 2947 | .name = "traceclk_src_fck", |
2948 | .ops = &clkops_null, | ||
2936 | .init = &omap2_init_clksel_parent, | 2949 | .init = &omap2_init_clksel_parent, |
2937 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2950 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
2938 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | 2951 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, |
2939 | .clksel = emu_src_clksel, | 2952 | .clksel = emu_src_clksel, |
2940 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 2953 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
2941 | .clkdm_name = "emu_clkdm", | 2954 | .clkdm_name = "emu_clkdm", |
2942 | .recalc = &omap2_clksel_recalc, | 2955 | .recalc = &omap2_clksel_recalc, |
2943 | }; | 2956 | }; |
@@ -2956,11 +2969,12 @@ static const struct clksel traceclk_clksel[] = { | |||
2956 | 2969 | ||
2957 | static struct clk traceclk_fck = { | 2970 | static struct clk traceclk_fck = { |
2958 | .name = "traceclk_fck", | 2971 | .name = "traceclk_fck", |
2972 | .ops = &clkops_null, | ||
2959 | .init = &omap2_init_clksel_parent, | 2973 | .init = &omap2_init_clksel_parent, |
2960 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2974 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
2961 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | 2975 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, |
2962 | .clksel = traceclk_clksel, | 2976 | .clksel = traceclk_clksel, |
2963 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | 2977 | .flags = CLOCK_IN_OMAP343X, |
2964 | .clkdm_name = "emu_clkdm", | 2978 | .clkdm_name = "emu_clkdm", |
2965 | .recalc = &omap2_clksel_recalc, | 2979 | .recalc = &omap2_clksel_recalc, |
2966 | }; | 2980 | }; |
@@ -2989,6 +3003,7 @@ static struct clk sr2_fck = { | |||
2989 | 3003 | ||
2990 | static struct clk sr_l4_ick = { | 3004 | static struct clk sr_l4_ick = { |
2991 | .name = "sr_l4_ick", | 3005 | .name = "sr_l4_ick", |
3006 | .ops = &clkops_null, /* RMK: missing? */ | ||
2992 | .parent = &l4_ick, | 3007 | .parent = &l4_ick, |
2993 | .flags = CLOCK_IN_OMAP343X, | 3008 | .flags = CLOCK_IN_OMAP343X, |
2994 | .clkdm_name = "core_l4_clkdm", | 3009 | .clkdm_name = "core_l4_clkdm", |
@@ -3000,15 +3015,17 @@ static struct clk sr_l4_ick = { | |||
3000 | /* XXX This clock no longer exists in 3430 TRM rev F */ | 3015 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
3001 | static struct clk gpt12_fck = { | 3016 | static struct clk gpt12_fck = { |
3002 | .name = "gpt12_fck", | 3017 | .name = "gpt12_fck", |
3018 | .ops = &clkops_null, | ||
3003 | .parent = &secure_32k_fck, | 3019 | .parent = &secure_32k_fck, |
3004 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | 3020 | .flags = CLOCK_IN_OMAP343X, |
3005 | .recalc = &followparent_recalc, | 3021 | .recalc = &followparent_recalc, |
3006 | }; | 3022 | }; |
3007 | 3023 | ||
3008 | static struct clk wdt1_fck = { | 3024 | static struct clk wdt1_fck = { |
3009 | .name = "wdt1_fck", | 3025 | .name = "wdt1_fck", |
3026 | .ops = &clkops_null, | ||
3010 | .parent = &secure_32k_fck, | 3027 | .parent = &secure_32k_fck, |
3011 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | 3028 | .flags = CLOCK_IN_OMAP343X, |
3012 | .recalc = &followparent_recalc, | 3029 | .recalc = &followparent_recalc, |
3013 | }; | 3030 | }; |
3014 | 3031 | ||