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authorPaul Walmsley <paul@pwsan.com>2008-07-03 05:24:45 -0400
committerTony Lindgren <tony@atomide.com>2008-07-03 05:24:45 -0400
commit542313cc98e72d026d2df86f515699dfaface460 (patch)
tree94bc87268a67cd1fff2d63cf48761f137384607d /arch/arm/mach-omap2/clock34xx.h
parent097c584cd48844d9ef8402bdc6ab49e7e2135f31 (diff)
ARM: OMAP2: Clock: Add OMAP3 DPLL autoidle functions
This patch adds support for DPLL autoidle control to the OMAP3 clock framework. These functions will be used by the noncore DPLL enable and disable code - this is because, according to the CDP code, the DPLL autoidle status must be saved and restored across DPLL lock/bypass/off transitions. N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather than just two. This code currently does not support the third option, low-power bypass autoidle. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r--arch/arm/mach-omap2/clock34xx.h83
1 files changed, 64 insertions, 19 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 73624dc04c97..e349d48ee807 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,14 +1,19 @@
1/* 1/*
2 * OMAP3 clock framework 2 * OMAP3 clock framework
3 * 3 *
4 * Virtual clocks are introduced as a convenient tools.
5 * They are sources for other clocks and not supposed
6 * to be requested from drivers directly.
7 *
8 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation 5 * Copyright (C) 2007-2008 Nokia Corporation
10 * 6 *
11 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
12 */ 17 */
13 18
14#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H 19#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
@@ -24,6 +29,11 @@
24 29
25static void omap3_dpll_recalc(struct clk *clk); 30static void omap3_dpll_recalc(struct clk *clk);
26static void omap3_clkoutx2_recalc(struct clk *clk); 31static void omap3_clkoutx2_recalc(struct clk *clk);
32static void omap3_dpll_allow_idle(struct clk *clk);
33static void omap3_dpll_deny_idle(struct clk *clk);
34static u32 omap3_dpll_autoidle_read(struct clk *clk);
35static int omap3_noncore_dpll_enable(struct clk *clk);
36static void omap3_noncore_dpll_disable(struct clk *clk);
27 37
28/* 38/*
29 * DPLL1 supplies clock to the MPU. 39 * DPLL1 supplies clock to the MPU.
@@ -33,6 +43,11 @@ static void omap3_clkoutx2_recalc(struct clk *clk);
33 * DPLL5 supplies other peripheral clocks (USBHOST, USIM). 43 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
34 */ 44 */
35 45
46/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
47#define DPLL_LOW_POWER_STOP 0x1
48#define DPLL_LOW_POWER_BYPASS 0x5
49#define DPLL_LOCKED 0x7
50
36/* PRM CLOCKS */ 51/* PRM CLOCKS */
37 52
38/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ 53/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
@@ -246,9 +261,14 @@ static const struct dpll_data dpll1_dd = {
246 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, 261 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
247 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), 262 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
248 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, 263 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
264 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
249 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, 265 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
250 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, 266 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
251 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, 267 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
268 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
269 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
270 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
271 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT,
252}; 272};
253 273
254static struct clk dpll1_ck = { 274static struct clk dpll1_ck = {
@@ -303,16 +323,24 @@ static const struct dpll_data dpll2_dd = {
303 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, 323 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
304 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), 324 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
305 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, 325 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
326 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
327 (1 << DPLL_LOW_POWER_BYPASS),
306 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, 328 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
307 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, 329 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
308 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, 330 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
331 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
332 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
333 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
334 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT
309}; 335};
310 336
311static struct clk dpll2_ck = { 337static struct clk dpll2_ck = {
312 .name = "dpll2_ck", 338 .name = "dpll2_ck",
313 .parent = &sys_ck, 339 .parent = &sys_ck,
314 .dpll_data = &dpll2_dd, 340 .dpll_data = &dpll2_dd,
315 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 341 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
342 .enable = &omap3_noncore_dpll_enable,
343 .disable = &omap3_noncore_dpll_disable,
316 .recalc = &omap3_dpll_recalc, 344 .recalc = &omap3_dpll_recalc,
317}; 345};
318 346
@@ -338,9 +366,11 @@ static struct clk dpll2_m2_ck = {
338 .recalc = &omap2_clksel_recalc, 366 .recalc = &omap2_clksel_recalc,
339}; 367};
340 368
341/* DPLL3 */ 369/*
342/* Source clock for all interfaces and for some device fclks */ 370 * DPLL3
343/* Type: DPLL */ 371 * Source clock for all interfaces and for some device fclks
372 * REVISIT: Also supports fast relock bypass - not included below
373 */
344static const struct dpll_data dpll3_dd = { 374static const struct dpll_data dpll3_dd = {
345 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 375 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
346 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, 376 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
@@ -350,6 +380,8 @@ static const struct dpll_data dpll3_dd = {
350 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, 380 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, 381 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, 382 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
383 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
384 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
353}; 385};
354 386
355static struct clk dpll3_ck = { 387static struct clk dpll3_ck = {
@@ -439,7 +471,7 @@ static struct clk core_ck = {
439 .name = "core_ck", 471 .name = "core_ck",
440 .init = &omap2_init_clksel_parent, 472 .init = &omap2_init_clksel_parent,
441 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 473 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
442 .clksel_mask = OMAP3430_ST_CORE_CLK, 474 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
443 .clksel = core_ck_clksel, 475 .clksel = core_ck_clksel,
444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 476 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
445 PARENT_CONTROLS_CLOCK, 477 PARENT_CONTROLS_CLOCK,
@@ -456,7 +488,7 @@ static struct clk dpll3_m2x2_ck = {
456 .name = "dpll3_m2x2_ck", 488 .name = "dpll3_m2x2_ck",
457 .init = &omap2_init_clksel_parent, 489 .init = &omap2_init_clksel_parent,
458 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 490 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
459 .clksel_mask = OMAP3430_ST_CORE_CLK, 491 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
460 .clksel = dpll3_m2x2_ck_clksel, 492 .clksel = dpll3_m2x2_ck_clksel,
461 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 493 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
462 PARENT_CONTROLS_CLOCK, 494 PARENT_CONTROLS_CLOCK,
@@ -503,7 +535,7 @@ static struct clk emu_core_alwon_ck = {
503 .parent = &dpll3_m3x2_ck, 535 .parent = &dpll3_m3x2_ck,
504 .init = &omap2_init_clksel_parent, 536 .init = &omap2_init_clksel_parent,
505 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 537 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
506 .clksel_mask = OMAP3430_ST_CORE_CLK, 538 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
507 .clksel = emu_core_alwon_ck_clksel, 539 .clksel = emu_core_alwon_ck_clksel,
508 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 540 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
509 PARENT_CONTROLS_CLOCK, 541 PARENT_CONTROLS_CLOCK,
@@ -519,16 +551,23 @@ static const struct dpll_data dpll4_dd = {
519 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, 551 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
520 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 552 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
521 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, 553 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
554 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
522 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, 555 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
523 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, 556 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
524 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, 557 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
558 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
559 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
560 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
561 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT,
525}; 562};
526 563
527static struct clk dpll4_ck = { 564static struct clk dpll4_ck = {
528 .name = "dpll4_ck", 565 .name = "dpll4_ck",
529 .parent = &sys_ck, 566 .parent = &sys_ck,
530 .dpll_data = &dpll4_dd, 567 .dpll_data = &dpll4_dd,
531 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 568 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
569 .enable = &omap3_noncore_dpll_enable,
570 .disable = &omap3_noncore_dpll_disable,
532 .recalc = &omap3_dpll_recalc, 571 .recalc = &omap3_dpll_recalc,
533}; 572};
534 573
@@ -584,7 +623,7 @@ static struct clk omap_96m_alwon_fck = {
584 .parent = &dpll4_m2x2_ck, 623 .parent = &dpll4_m2x2_ck,
585 .init = &omap2_init_clksel_parent, 624 .init = &omap2_init_clksel_parent,
586 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 625 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
587 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 626 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
588 .clksel = omap_96m_alwon_fck_clksel, 627 .clksel = omap_96m_alwon_fck_clksel,
589 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 628 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
590 PARENT_CONTROLS_CLOCK, 629 PARENT_CONTROLS_CLOCK,
@@ -610,7 +649,7 @@ static struct clk cm_96m_fck = {
610 .parent = &dpll4_m2x2_ck, 649 .parent = &dpll4_m2x2_ck,
611 .init = &omap2_init_clksel_parent, 650 .init = &omap2_init_clksel_parent,
612 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 651 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
613 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 652 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
614 .clksel = cm_96m_fck_clksel, 653 .clksel = cm_96m_fck_clksel,
615 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 654 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
616 PARENT_CONTROLS_CLOCK, 655 PARENT_CONTROLS_CLOCK,
@@ -652,7 +691,7 @@ static struct clk virt_omap_54m_fck = {
652 .parent = &dpll4_m3x2_ck, 691 .parent = &dpll4_m3x2_ck,
653 .init = &omap2_init_clksel_parent, 692 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 693 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 694 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
656 .clksel = virt_omap_54m_fck_clksel, 695 .clksel = virt_omap_54m_fck_clksel,
657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 696 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
658 PARENT_CONTROLS_CLOCK, 697 PARENT_CONTROLS_CLOCK,
@@ -810,17 +849,23 @@ static const struct dpll_data dpll5_dd = {
810 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, 849 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
811 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), 850 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
812 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, 851 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
852 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
813 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, 853 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
814 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, 854 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
815 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, 855 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
856 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
857 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
858 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
859 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
816}; 860};
817 861
818static struct clk dpll5_ck = { 862static struct clk dpll5_ck = {
819 .name = "dpll5_ck", 863 .name = "dpll5_ck",
820 .parent = &sys_ck, 864 .parent = &sys_ck,
821 .dpll_data = &dpll5_dd, 865 .dpll_data = &dpll5_dd,
822 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 866 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
823 ALWAYS_ENABLED, 867 .enable = &omap3_noncore_dpll_enable,
868 .disable = &omap3_noncore_dpll_disable,
824 .recalc = &omap3_dpll_recalc, 869 .recalc = &omap3_dpll_recalc,
825}; 870};
826 871
@@ -1939,7 +1984,7 @@ static struct clk dss1_alwon_fck = {
1939 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 1984 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1940 .enable_bit = OMAP3430_EN_DSS1_SHIFT, 1985 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1941 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 1986 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1942 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 1987 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
1943 .clksel = dss1_alwon_fck_clksel, 1988 .clksel = dss1_alwon_fck_clksel,
1944 .flags = CLOCK_IN_OMAP343X, 1989 .flags = CLOCK_IN_OMAP343X,
1945 .recalc = &omap2_clksel_recalc, 1990 .recalc = &omap2_clksel_recalc,
@@ -1995,7 +2040,7 @@ static struct clk cam_mclk = {
1995 .parent = &dpll4_m5x2_ck, 2040 .parent = &dpll4_m5x2_ck,
1996 .init = &omap2_init_clksel_parent, 2041 .init = &omap2_init_clksel_parent,
1997 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 2042 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1998 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 2043 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
1999 .clksel = cam_mclk_clksel, 2044 .clksel = cam_mclk_clksel,
2000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2045 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2001 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2046 .enable_bit = OMAP3430_EN_CAM_SHIFT,