diff options
author | Rajendra Nayak <rnayak@ti.com> | 2009-12-08 20:47:16 -0500 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-12-11 19:00:46 -0500 |
commit | a1391d276866845018920329bc2a3a82ab322af8 (patch) | |
tree | a16a46b6d0af3cb5e3dcd4f7de207f138d087011 /arch/arm/mach-omap2/clock34xx.h | |
parent | d79b126724554122d9598834ef39fb0bb4fc132d (diff) |
ARM: OMAP4: PM: Move DPLL control apis to dpll.c
This patch moves all the dpll control api's to a
common file dpll.c. This is in preperation of omap4
support wherein most of these api's can be reused.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index b08809efb0c8..9a2c07eac9ad 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -8,21 +8,10 @@ | |||
8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H | 8 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H |
9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H | 9 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H |
10 | 10 | ||
11 | unsigned long omap3_dpll_recalc(struct clk *clk); | ||
12 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); | ||
13 | void omap3_dpll_allow_idle(struct clk *clk); | ||
14 | void omap3_dpll_deny_idle(struct clk *clk); | ||
15 | u32 omap3_dpll_autoidle_read(struct clk *clk); | ||
16 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); | ||
17 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); | 11 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); |
18 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | 12 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); |
19 | void omap3_clk_lock_dpll5(void); | 13 | void omap3_clk_lock_dpll5(void); |
20 | 14 | ||
21 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ | ||
22 | #define DPLL_LOW_POWER_STOP 0x1 | ||
23 | #define DPLL_LOW_POWER_BYPASS 0x5 | ||
24 | #define DPLL_LOCKED 0x7 | ||
25 | |||
26 | extern struct clk *sdrc_ick_p; | 15 | extern struct clk *sdrc_ick_p; |
27 | extern struct clk *arm_fck_p; | 16 | extern struct clk *arm_fck_p; |
28 | 17 | ||