diff options
author | Paul Walmsley <paul@pwsan.com> | 2009-12-08 18:18:47 -0500 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-12-11 18:12:15 -0500 |
commit | 82e9bd588563c4e22ebb55b684ebec7e310cc715 (patch) | |
tree | cad50e0c12980a14de3531ec7bf78e3f3e4a3313 /arch/arm/mach-omap2/clock34xx.c | |
parent | 75d43340113e3822e390f644e8b197737e4c553e (diff) |
OMAP3 clock: convert clock34xx.h to clock34xx_data.c
The OMAP3 clock code currently #includes a large .h file full of static
data structures. Instead, define the data in a .c file.
Russell King <linux@arm.linux.org.uk> proposed this new arrangement:
http://marc.info/?l=linux-omap&m=125967425908895&w=2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Russell King <linux@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.c')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 452 |
1 files changed, 66 insertions, 386 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 3344809e5fe5..6dc46dc1ea3a 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -30,292 +30,19 @@ | |||
30 | #include <plat/cpu.h> | 30 | #include <plat/cpu.h> |
31 | #include <plat/clock.h> | 31 | #include <plat/clock.h> |
32 | #include <plat/sram.h> | 32 | #include <plat/sram.h> |
33 | #include <plat/sdrc.h> | ||
33 | #include <asm/div64.h> | 34 | #include <asm/div64.h> |
34 | #include <asm/clkdev.h> | 35 | #include <asm/clkdev.h> |
35 | 36 | ||
36 | #include <plat/sdrc.h> | 37 | #include <plat/sdrc.h> |
37 | #include "clock.h" | 38 | #include "clock.h" |
39 | #include "clock34xx.h" | ||
40 | #include "sdrc.h" | ||
38 | #include "prm.h" | 41 | #include "prm.h" |
39 | #include "prm-regbits-34xx.h" | 42 | #include "prm-regbits-34xx.h" |
40 | #include "cm.h" | 43 | #include "cm.h" |
41 | #include "cm-regbits-34xx.h" | 44 | #include "cm-regbits-34xx.h" |
42 | 45 | ||
43 | static const struct clkops clkops_noncore_dpll_ops; | ||
44 | |||
45 | static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, | ||
46 | void __iomem **idlest_reg, | ||
47 | u8 *idlest_bit); | ||
48 | static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, | ||
49 | void __iomem **idlest_reg, | ||
50 | u8 *idlest_bit); | ||
51 | static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | ||
52 | void __iomem **idlest_reg, | ||
53 | u8 *idlest_bit); | ||
54 | |||
55 | static const struct clkops clkops_omap3430es2_ssi_wait = { | ||
56 | .enable = omap2_dflt_clk_enable, | ||
57 | .disable = omap2_dflt_clk_disable, | ||
58 | .find_idlest = omap3430es2_clk_ssi_find_idlest, | ||
59 | .find_companion = omap2_clk_dflt_find_companion, | ||
60 | }; | ||
61 | |||
62 | static const struct clkops clkops_omap3430es2_hsotgusb_wait = { | ||
63 | .enable = omap2_dflt_clk_enable, | ||
64 | .disable = omap2_dflt_clk_disable, | ||
65 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, | ||
66 | .find_companion = omap2_clk_dflt_find_companion, | ||
67 | }; | ||
68 | |||
69 | static const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | ||
70 | .enable = omap2_dflt_clk_enable, | ||
71 | .disable = omap2_dflt_clk_disable, | ||
72 | .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, | ||
73 | .find_companion = omap2_clk_dflt_find_companion, | ||
74 | }; | ||
75 | |||
76 | #include "clock34xx.h" | ||
77 | |||
78 | struct omap_clk { | ||
79 | u32 cpu; | ||
80 | struct clk_lookup lk; | ||
81 | }; | ||
82 | |||
83 | #define CLK(dev, con, ck, cp) \ | ||
84 | { \ | ||
85 | .cpu = cp, \ | ||
86 | .lk = { \ | ||
87 | .dev_id = dev, \ | ||
88 | .con_id = con, \ | ||
89 | .clk = ck, \ | ||
90 | }, \ | ||
91 | } | ||
92 | |||
93 | #define CK_343X (1 << 0) | ||
94 | #define CK_3430ES1 (1 << 1) | ||
95 | #define CK_3430ES2 (1 << 2) | ||
96 | |||
97 | static struct omap_clk omap34xx_clks[] = { | ||
98 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), | ||
99 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), | ||
100 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), | ||
101 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), | ||
102 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), | ||
103 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), | ||
104 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), | ||
105 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), | ||
106 | CLK(NULL, "sys_ck", &sys_ck, CK_343X), | ||
107 | CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), | ||
108 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), | ||
109 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), | ||
110 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), | ||
111 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), | ||
112 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), | ||
113 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | ||
114 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | ||
115 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), | ||
116 | CLK(NULL, "core_ck", &core_ck, CK_343X), | ||
117 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), | ||
118 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), | ||
119 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), | ||
120 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), | ||
121 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), | ||
122 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), | ||
123 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), | ||
124 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), | ||
125 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), | ||
126 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), | ||
127 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), | ||
128 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), | ||
129 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), | ||
130 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), | ||
131 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), | ||
132 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), | ||
133 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), | ||
134 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), | ||
135 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), | ||
136 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), | ||
137 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), | ||
138 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), | ||
139 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), | ||
140 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), | ||
141 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), | ||
142 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), | ||
143 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), | ||
144 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), | ||
145 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), | ||
146 | CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), | ||
147 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), | ||
148 | CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), | ||
149 | CLK(NULL, "arm_fck", &arm_fck, CK_343X), | ||
150 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), | ||
151 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), | ||
152 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | ||
153 | CLK(NULL, "l3_ick", &l3_ick, CK_343X), | ||
154 | CLK(NULL, "l4_ick", &l4_ick, CK_343X), | ||
155 | CLK(NULL, "rm_ick", &rm_ick, CK_343X), | ||
156 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | ||
157 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | ||
158 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | ||
159 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | ||
160 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | ||
161 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), | ||
162 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), | ||
163 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | ||
164 | CLK(NULL, "modem_fck", &modem_fck, CK_343X), | ||
165 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), | ||
166 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), | ||
167 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), | ||
168 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), | ||
169 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), | ||
170 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), | ||
171 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), | ||
172 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), | ||
173 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), | ||
174 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), | ||
175 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), | ||
176 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), | ||
177 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), | ||
178 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), | ||
179 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), | ||
180 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), | ||
181 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), | ||
182 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), | ||
183 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), | ||
184 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), | ||
185 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), | ||
186 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), | ||
187 | CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), | ||
188 | CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), | ||
189 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | ||
190 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), | ||
191 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), | ||
192 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), | ||
193 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), | ||
194 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), | ||
195 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), | ||
196 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), | ||
197 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), | ||
198 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), | ||
199 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), | ||
200 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | ||
201 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | ||
202 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | ||
203 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), | ||
204 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), | ||
205 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), | ||
206 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), | ||
207 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), | ||
208 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), | ||
209 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | ||
210 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), | ||
211 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), | ||
212 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), | ||
213 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), | ||
214 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), | ||
215 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), | ||
216 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), | ||
217 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), | ||
218 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), | ||
219 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), | ||
220 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), | ||
221 | CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), | ||
222 | CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), | ||
223 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), | ||
224 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), | ||
225 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), | ||
226 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), | ||
227 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | ||
228 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | ||
229 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), | ||
230 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | ||
231 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), | ||
232 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), | ||
233 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), | ||
234 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), | ||
235 | CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), | ||
236 | CLK("omap_rng", "ick", &rng_ick, CK_343X), | ||
237 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | ||
238 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | ||
239 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), | ||
240 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), | ||
241 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), | ||
242 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), | ||
243 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), | ||
244 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), | ||
245 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), | ||
246 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | ||
247 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | ||
248 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | ||
249 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), | ||
250 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), | ||
251 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), | ||
252 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), | ||
253 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), | ||
254 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), | ||
255 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), | ||
256 | CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), | ||
257 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), | ||
258 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | ||
259 | CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), | ||
260 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), | ||
261 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), | ||
262 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), | ||
263 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), | ||
264 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), | ||
265 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), | ||
266 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), | ||
267 | CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), | ||
268 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), | ||
269 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), | ||
270 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), | ||
271 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), | ||
272 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), | ||
273 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), | ||
274 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), | ||
275 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), | ||
276 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), | ||
277 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), | ||
278 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), | ||
279 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), | ||
280 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), | ||
281 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), | ||
282 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), | ||
283 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), | ||
284 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), | ||
285 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), | ||
286 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), | ||
287 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), | ||
288 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), | ||
289 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), | ||
290 | CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), | ||
291 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), | ||
292 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), | ||
293 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), | ||
294 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), | ||
295 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), | ||
296 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), | ||
297 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), | ||
298 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), | ||
299 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), | ||
300 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), | ||
301 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), | ||
302 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), | ||
303 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), | ||
304 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), | ||
305 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), | ||
306 | CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), | ||
307 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), | ||
308 | CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), | ||
309 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), | ||
310 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), | ||
311 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | ||
312 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | ||
313 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | ||
314 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), | ||
315 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), | ||
316 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), | ||
317 | }; | ||
318 | |||
319 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | 46 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ |
320 | #define DPLL_AUTOIDLE_DISABLE 0x0 | 47 | #define DPLL_AUTOIDLE_DISABLE 0x0 |
321 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | 48 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 |
@@ -331,6 +58,9 @@ static struct omap_clk omap34xx_clks[] = { | |||
331 | */ | 58 | */ |
332 | #define DPLL5_FREQ_FOR_USBHOST 120000000 | 59 | #define DPLL5_FREQ_FOR_USBHOST 120000000 |
333 | 60 | ||
61 | /* needed by omap3_core_dpll_m2_set_rate() */ | ||
62 | struct clk *sdrc_ick_p, *arm_fck_p; | ||
63 | |||
334 | /** | 64 | /** |
335 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI | 65 | * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI |
336 | * @clk: struct clk * being enabled | 66 | * @clk: struct clk * being enabled |
@@ -352,6 +82,13 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, | |||
352 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; | 82 | *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; |
353 | } | 83 | } |
354 | 84 | ||
85 | const struct clkops clkops_omap3430es2_ssi_wait = { | ||
86 | .enable = omap2_dflt_clk_enable, | ||
87 | .disable = omap2_dflt_clk_disable, | ||
88 | .find_idlest = omap3430es2_clk_ssi_find_idlest, | ||
89 | .find_companion = omap2_clk_dflt_find_companion, | ||
90 | }; | ||
91 | |||
355 | /** | 92 | /** |
356 | * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST | 93 | * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST |
357 | * @clk: struct clk * being enabled | 94 | * @clk: struct clk * being enabled |
@@ -377,6 +114,13 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, | |||
377 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; | 114 | *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; |
378 | } | 115 | } |
379 | 116 | ||
117 | const struct clkops clkops_omap3430es2_dss_usbhost_wait = { | ||
118 | .enable = omap2_dflt_clk_enable, | ||
119 | .disable = omap2_dflt_clk_disable, | ||
120 | .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, | ||
121 | .find_companion = omap2_clk_dflt_find_companion, | ||
122 | }; | ||
123 | |||
380 | /** | 124 | /** |
381 | * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB | 125 | * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB |
382 | * @clk: struct clk * being enabled | 126 | * @clk: struct clk * being enabled |
@@ -398,13 +142,20 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, | |||
398 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; | 142 | *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; |
399 | } | 143 | } |
400 | 144 | ||
145 | const struct clkops clkops_omap3430es2_hsotgusb_wait = { | ||
146 | .enable = omap2_dflt_clk_enable, | ||
147 | .disable = omap2_dflt_clk_disable, | ||
148 | .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, | ||
149 | .find_companion = omap2_clk_dflt_find_companion, | ||
150 | }; | ||
151 | |||
401 | /** | 152 | /** |
402 | * omap3_dpll_recalc - recalculate DPLL rate | 153 | * omap3_dpll_recalc - recalculate DPLL rate |
403 | * @clk: DPLL struct clk | 154 | * @clk: DPLL struct clk |
404 | * | 155 | * |
405 | * Recalculate and propagate the DPLL rate. | 156 | * Recalculate and propagate the DPLL rate. |
406 | */ | 157 | */ |
407 | static unsigned long omap3_dpll_recalc(struct clk *clk) | 158 | unsigned long omap3_dpll_recalc(struct clk *clk) |
408 | { | 159 | { |
409 | return omap2_get_dpll_rate(clk); | 160 | return omap2_get_dpll_rate(clk); |
410 | } | 161 | } |
@@ -628,24 +379,21 @@ static int omap3_noncore_dpll_enable(struct clk *clk) | |||
628 | } | 379 | } |
629 | 380 | ||
630 | /** | 381 | /** |
631 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | 382 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop |
632 | * @clk: pointer to a DPLL struct clk | 383 | * @clk: pointer to a DPLL struct clk |
633 | * | 384 | * |
634 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | 385 | * Instructs a non-CORE DPLL to enter low-power stop. This function is |
635 | * The choice of modes depends on the DPLL's programmed rate: if it is | 386 | * intended for use in struct clkops. No return value. |
636 | * the same as the DPLL's parent clock, it will enter bypass; | ||
637 | * otherwise, it will enter lock. This code will wait for the DPLL to | ||
638 | * indicate readiness before returning, unless the DPLL takes too long | ||
639 | * to enter the target state. Intended to be used as the struct clk's | ||
640 | * enable function. If DPLL3 was passed in, or the DPLL does not | ||
641 | * support low-power stop, or if the DPLL took too long to enter | ||
642 | * bypass or lock, return -EINVAL; otherwise, return 0. | ||
643 | */ | 387 | */ |
644 | static void omap3_noncore_dpll_disable(struct clk *clk) | 388 | static void omap3_noncore_dpll_disable(struct clk *clk) |
645 | { | 389 | { |
646 | _omap3_noncore_dpll_stop(clk); | 390 | _omap3_noncore_dpll_stop(clk); |
647 | } | 391 | } |
648 | 392 | ||
393 | const struct clkops clkops_noncore_dpll_ops = { | ||
394 | .enable = omap3_noncore_dpll_enable, | ||
395 | .disable = omap3_noncore_dpll_disable, | ||
396 | }; | ||
649 | 397 | ||
650 | /* Non-CORE DPLL rate set code */ | 398 | /* Non-CORE DPLL rate set code */ |
651 | 399 | ||
@@ -700,7 +448,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |||
700 | * target rate if it hasn't been done already, then program and lock | 448 | * target rate if it hasn't been done already, then program and lock |
701 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | 449 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. |
702 | */ | 450 | */ |
703 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | 451 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) |
704 | { | 452 | { |
705 | struct clk *new_parent = NULL; | 453 | struct clk *new_parent = NULL; |
706 | u16 freqsel; | 454 | u16 freqsel; |
@@ -771,7 +519,7 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |||
771 | return 0; | 519 | return 0; |
772 | } | 520 | } |
773 | 521 | ||
774 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | 522 | int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) |
775 | { | 523 | { |
776 | /* | 524 | /* |
777 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | 525 | * According to the 12-5 CDP code from TI, "Limitation 2.5" |
@@ -802,12 +550,12 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | |||
802 | * Program the DPLL M2 divider with the rounded target rate. Returns | 550 | * Program the DPLL M2 divider with the rounded target rate. Returns |
803 | * -EINVAL upon error, or 0 upon success. | 551 | * -EINVAL upon error, or 0 upon success. |
804 | */ | 552 | */ |
805 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | 553 | int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) |
806 | { | 554 | { |
807 | u32 new_div = 0; | 555 | u32 new_div = 0; |
808 | u32 unlock_dll = 0; | 556 | u32 unlock_dll = 0; |
809 | u32 c; | 557 | u32 c; |
810 | unsigned long validrate, sdrcrate, mpurate; | 558 | unsigned long validrate, sdrcrate, _mpurate; |
811 | struct omap_sdrc_params *sdrc_cs0; | 559 | struct omap_sdrc_params *sdrc_cs0; |
812 | struct omap_sdrc_params *sdrc_cs1; | 560 | struct omap_sdrc_params *sdrc_cs1; |
813 | int ret; | 561 | int ret; |
@@ -819,7 +567,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
819 | if (validrate != rate) | 567 | if (validrate != rate) |
820 | return -EINVAL; | 568 | return -EINVAL; |
821 | 569 | ||
822 | sdrcrate = sdrc_ick.rate; | 570 | sdrcrate = sdrc_ick_p->rate; |
823 | if (rate > clk->rate) | 571 | if (rate > clk->rate) |
824 | sdrcrate <<= ((rate / clk->rate) >> 1); | 572 | sdrcrate <<= ((rate / clk->rate) >> 1); |
825 | else | 573 | else |
@@ -837,8 +585,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
837 | /* | 585 | /* |
838 | * XXX This only needs to be done when the CPU frequency changes | 586 | * XXX This only needs to be done when the CPU frequency changes |
839 | */ | 587 | */ |
840 | mpurate = arm_fck.rate / CYCLES_PER_MHZ; | 588 | _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; |
841 | c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; | 589 | c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; |
842 | c += 1; /* for safety */ | 590 | c += 1; /* for safety */ |
843 | c *= SDRC_MPURATE_LOOPS; | 591 | c *= SDRC_MPURATE_LOOPS; |
844 | c >>= SDRC_MPURATE_SCALE; | 592 | c >>= SDRC_MPURATE_SCALE; |
@@ -875,11 +623,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
875 | } | 623 | } |
876 | 624 | ||
877 | 625 | ||
878 | static const struct clkops clkops_noncore_dpll_ops = { | ||
879 | .enable = &omap3_noncore_dpll_enable, | ||
880 | .disable = &omap3_noncore_dpll_disable, | ||
881 | }; | ||
882 | |||
883 | /* DPLL autoidle read/set code */ | 626 | /* DPLL autoidle read/set code */ |
884 | 627 | ||
885 | 628 | ||
@@ -891,7 +634,7 @@ static const struct clkops clkops_noncore_dpll_ops = { | |||
891 | * -EINVAL if passed a null pointer or if the struct clk does not | 634 | * -EINVAL if passed a null pointer or if the struct clk does not |
892 | * appear to refer to a DPLL. | 635 | * appear to refer to a DPLL. |
893 | */ | 636 | */ |
894 | static u32 omap3_dpll_autoidle_read(struct clk *clk) | 637 | u32 omap3_dpll_autoidle_read(struct clk *clk) |
895 | { | 638 | { |
896 | const struct dpll_data *dd; | 639 | const struct dpll_data *dd; |
897 | u32 v; | 640 | u32 v; |
@@ -917,7 +660,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) | |||
917 | * OMAP3430. The DPLL will enter low-power stop when its downstream | 660 | * OMAP3430. The DPLL will enter low-power stop when its downstream |
918 | * clocks are gated. No return value. | 661 | * clocks are gated. No return value. |
919 | */ | 662 | */ |
920 | static void omap3_dpll_allow_idle(struct clk *clk) | 663 | void omap3_dpll_allow_idle(struct clk *clk) |
921 | { | 664 | { |
922 | const struct dpll_data *dd; | 665 | const struct dpll_data *dd; |
923 | u32 v; | 666 | u32 v; |
@@ -944,7 +687,7 @@ static void omap3_dpll_allow_idle(struct clk *clk) | |||
944 | * | 687 | * |
945 | * Disable DPLL automatic idle control. No return value. | 688 | * Disable DPLL automatic idle control. No return value. |
946 | */ | 689 | */ |
947 | static void omap3_dpll_deny_idle(struct clk *clk) | 690 | void omap3_dpll_deny_idle(struct clk *clk) |
948 | { | 691 | { |
949 | const struct dpll_data *dd; | 692 | const struct dpll_data *dd; |
950 | u32 v; | 693 | u32 v; |
@@ -969,7 +712,7 @@ static void omap3_dpll_deny_idle(struct clk *clk) | |||
969 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | 712 | * Using parent clock DPLL data, look up DPLL state. If locked, set our |
970 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | 713 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. |
971 | */ | 714 | */ |
972 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk) | 715 | unsigned long omap3_clkoutx2_recalc(struct clk *clk) |
973 | { | 716 | { |
974 | const struct dpll_data *dd; | 717 | const struct dpll_data *dd; |
975 | unsigned long rate; | 718 | unsigned long rate; |
@@ -1005,7 +748,7 @@ static unsigned long omap3_clkoutx2_recalc(struct clk *clk) | |||
1005 | */ | 748 | */ |
1006 | #if defined(CONFIG_ARCH_OMAP3) | 749 | #if defined(CONFIG_ARCH_OMAP3) |
1007 | 750 | ||
1008 | static struct clk_functions omap2_clk_functions = { | 751 | struct clk_functions omap2_clk_functions = { |
1009 | .clk_enable = omap2_clk_enable, | 752 | .clk_enable = omap2_clk_enable, |
1010 | .clk_disable = omap2_clk_disable, | 753 | .clk_disable = omap2_clk_disable, |
1011 | .clk_round_rate = omap2_clk_round_rate, | 754 | .clk_round_rate = omap2_clk_round_rate, |
@@ -1031,7 +774,7 @@ void omap2_clk_prepare_for_reboot(void) | |||
1031 | #endif | 774 | #endif |
1032 | } | 775 | } |
1033 | 776 | ||
1034 | static void omap3_clk_lock_dpll5(void) | 777 | void omap3_clk_lock_dpll5(void) |
1035 | { | 778 | { |
1036 | struct clk *dpll5_clk; | 779 | struct clk *dpll5_clk; |
1037 | struct clk *dpll5_m2_clk; | 780 | struct clk *dpll5_m2_clk; |
@@ -1061,19 +804,32 @@ static void omap3_clk_lock_dpll5(void) | |||
1061 | */ | 804 | */ |
1062 | static int __init omap2_clk_arch_init(void) | 805 | static int __init omap2_clk_arch_init(void) |
1063 | { | 806 | { |
807 | struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck; | ||
808 | unsigned long osc_sys_rate; | ||
809 | |||
1064 | if (!mpurate) | 810 | if (!mpurate) |
1065 | return -EINVAL; | 811 | return -EINVAL; |
1066 | 812 | ||
813 | /* XXX test these for success */ | ||
814 | dpll1_ck = clk_get(NULL, "dpll1_ck"); | ||
815 | arm_fck = clk_get(NULL, "arm_fck"); | ||
816 | core_ck = clk_get(NULL, "core_ck"); | ||
817 | osc_sys_ck = clk_get(NULL, "osc_sys_ck"); | ||
818 | |||
1067 | /* REVISIT: not yet ready for 343x */ | 819 | /* REVISIT: not yet ready for 343x */ |
1068 | if (clk_set_rate(&dpll1_ck, mpurate)) | 820 | if (clk_set_rate(dpll1_ck, mpurate)) |
1069 | printk(KERN_ERR "*** Unable to set MPU rate\n"); | 821 | printk(KERN_ERR "*** Unable to set MPU rate\n"); |
1070 | 822 | ||
1071 | recalculate_root_clocks(); | 823 | recalculate_root_clocks(); |
1072 | 824 | ||
1073 | printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): " | 825 | osc_sys_rate = clk_get_rate(osc_sys_ck); |
1074 | "%ld.%01ld/%ld/%ld MHz\n", | 826 | |
1075 | (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10), | 827 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): " |
1076 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ; | 828 | "%ld.%01ld/%ld/%ld MHz\n", |
829 | (osc_sys_rate / 1000000), | ||
830 | ((osc_sys_rate / 100000) % 10), | ||
831 | (clk_get_rate(core_ck) / 1000000), | ||
832 | (clk_get_rate(arm_fck) / 1000000)); | ||
1077 | 833 | ||
1078 | calibrate_delay(); | 834 | calibrate_delay(); |
1079 | 835 | ||
@@ -1081,83 +837,7 @@ static int __init omap2_clk_arch_init(void) | |||
1081 | } | 837 | } |
1082 | arch_initcall(omap2_clk_arch_init); | 838 | arch_initcall(omap2_clk_arch_init); |
1083 | 839 | ||
1084 | int __init omap2_clk_init(void) | ||
1085 | { | ||
1086 | /* struct prcm_config *prcm; */ | ||
1087 | struct omap_clk *c; | ||
1088 | /* u32 clkrate; */ | ||
1089 | u32 cpu_clkflg; | ||
1090 | |||
1091 | if (cpu_is_omap34xx()) { | ||
1092 | cpu_mask = RATE_IN_343X; | ||
1093 | cpu_clkflg = CK_343X; | ||
1094 | 840 | ||
1095 | /* | ||
1096 | * Update this if there are further clock changes between ES2 | ||
1097 | * and production parts | ||
1098 | */ | ||
1099 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
1100 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ | ||
1101 | cpu_clkflg |= CK_3430ES1; | ||
1102 | } else { | ||
1103 | cpu_mask |= RATE_IN_3430ES2; | ||
1104 | cpu_clkflg |= CK_3430ES2; | ||
1105 | } | ||
1106 | } | ||
1107 | |||
1108 | clk_init(&omap2_clk_functions); | ||
1109 | |||
1110 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | ||
1111 | clk_preinit(c->lk.clk); | ||
1112 | |||
1113 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | ||
1114 | if (c->cpu & cpu_clkflg) { | ||
1115 | clkdev_add(&c->lk); | ||
1116 | clk_register(c->lk.clk); | ||
1117 | omap2_init_clk_clkdm(c->lk.clk); | ||
1118 | } | ||
1119 | |||
1120 | /* REVISIT: Not yet ready for OMAP3 */ | ||
1121 | #if 0 | ||
1122 | /* Check the MPU rate set by bootloader */ | ||
1123 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
1124 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
1125 | if (!(prcm->flags & cpu_mask)) | ||
1126 | continue; | ||
1127 | if (prcm->xtal_speed != sys_ck.rate) | ||
1128 | continue; | ||
1129 | if (prcm->dpll_speed <= clkrate) | ||
1130 | break; | ||
1131 | } | ||
1132 | curr_prcm_set = prcm; | ||
1133 | #endif | 841 | #endif |
1134 | 842 | ||
1135 | recalculate_root_clocks(); | ||
1136 | |||
1137 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " | ||
1138 | "%ld.%01ld/%ld/%ld MHz\n", | ||
1139 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | ||
1140 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); | ||
1141 | |||
1142 | /* | ||
1143 | * Only enable those clocks we will need, let the drivers | ||
1144 | * enable other clocks as necessary | ||
1145 | */ | ||
1146 | clk_enable_init_clocks(); | ||
1147 | |||
1148 | /* | ||
1149 | * Lock DPLL5 and put it in autoidle. | ||
1150 | */ | ||
1151 | if (omap_rev() >= OMAP3430_REV_ES2_0) | ||
1152 | omap3_clk_lock_dpll5(); | ||
1153 | |||
1154 | /* Avoid sleeping during omap2_clk_prepare_for_reboot() */ | ||
1155 | /* REVISIT: not yet ready for 343x */ | ||
1156 | #if 0 | ||
1157 | vclk = clk_get(NULL, "virt_prcm_set"); | ||
1158 | sclk = clk_get(NULL, "sys_ck"); | ||
1159 | #endif | ||
1160 | return 0; | ||
1161 | } | ||
1162 | 843 | ||
1163 | #endif | ||