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authorIngo Molnar <mingo@elte.hu>2009-07-01 03:56:10 -0400
committerIngo Molnar <mingo@elte.hu>2009-07-01 03:56:26 -0400
commit087021ba41e9481202103d51d3dd0c4706899a2b (patch)
treebf5d67420fd176682a1f8f1e9342ad397c23937a /arch/arm/mach-omap2/clock34xx.c
parentfb9c818873a788c5c01c9868cc6050df96e2c7df (diff)
parente83c2b0ff325f52dda1aff3572d0e1516216c54b (diff)
Merge branch 'linus' into perfcounters/urgent
Merge reason: this branch was on a .30-ish base before, update it to an almost-.31-rc2 upstream base to pick up fixes. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.c')
-rw-r--r--arch/arm/mach-omap2/clock34xx.c42
1 files changed, 31 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 9e43fe5209d3..045da923e75b 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = {
286 286
287#define MIN_SDRC_DLL_LOCK_FREQ 83000000 287#define MIN_SDRC_DLL_LOCK_FREQ 83000000
288 288
289#define CYCLES_PER_MHZ 1000000
290
291/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
292#define SDRC_MPURATE_SCALE 8
293
294/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
295#define SDRC_MPURATE_BASE_SHIFT 9
296
297/*
298 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
299 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
300 */
301#define SDRC_MPURATE_LOOPS 96
302
289/** 303/**
290 * omap3_dpll_recalc - recalculate DPLL rate 304 * omap3_dpll_recalc - recalculate DPLL rate
291 * @clk: DPLL struct clk 305 * @clk: DPLL struct clk
@@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
709{ 723{
710 u32 new_div = 0; 724 u32 new_div = 0;
711 u32 unlock_dll = 0; 725 u32 unlock_dll = 0;
712 unsigned long validrate, sdrcrate; 726 u32 c;
727 unsigned long validrate, sdrcrate, mpurate;
713 struct omap_sdrc_params *sp; 728 struct omap_sdrc_params *sp;
714 729
715 if (!clk || !rate) 730 if (!clk || !rate)
@@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
718 if (clk != &dpll3_m2_ck) 733 if (clk != &dpll3_m2_ck)
719 return -EINVAL; 734 return -EINVAL;
720 735
721 if (rate == clk->rate)
722 return 0;
723
724 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 736 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
725 if (validrate != rate) 737 if (validrate != rate)
726 return -EINVAL; 738 return -EINVAL;
727 739
728 sdrcrate = sdrc_ick.rate; 740 sdrcrate = sdrc_ick.rate;
729 if (rate > clk->rate) 741 if (rate > clk->rate)
730 sdrcrate <<= ((rate / clk->rate) - 1); 742 sdrcrate <<= ((rate / clk->rate) >> 1);
731 else 743 else
732 sdrcrate >>= ((clk->rate / rate) - 1); 744 sdrcrate >>= ((clk->rate / rate) >> 1);
733 745
734 sp = omap2_sdrc_get_params(sdrcrate); 746 sp = omap2_sdrc_get_params(sdrcrate);
735 if (!sp) 747 if (!sp)
@@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
740 unlock_dll = 1; 752 unlock_dll = 1;
741 } 753 }
742 754
755 /*
756 * XXX This only needs to be done when the CPU frequency changes
757 */
758 mpurate = arm_fck.rate / CYCLES_PER_MHZ;
759 c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
760 c += 1; /* for safety */
761 c *= SDRC_MPURATE_LOOPS;
762 c >>= SDRC_MPURATE_SCALE;
763 if (c == 0)
764 c = 1;
765
743 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, 766 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
744 validrate); 767 validrate);
745 pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", 768 pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
746 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); 769 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
747 770
748 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
749 WARN_ON(new_div != 1 && new_div != 2);
750
751 /* REVISIT: Add SDRC_MR changing to this code also */
752 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, 771 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
753 sp->actim_ctrlb, new_div, unlock_dll); 772 sp->actim_ctrlb, new_div, unlock_dll, c,
773 sp->mr, rate > clk->rate);
754 774
755 return 0; 775 return 0;
756} 776}