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authorPaul Walmsley <paul@pwsan.com>2010-01-26 22:13:11 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-29 12:14:22 -0500
commitfeec1277a5c599ebca6217bc6bb9f6410e84793b (patch)
treecd095939bdd63b102b235857d434c1890aba8450 /arch/arm/mach-omap2/clock34xx.c
parentda4d2904abc0c31ac829e9c6d52106d5a6606507 (diff)
OMAP2/3/4 clock: omap2_clk_prepare_for_reboot() is OMAP2xxx-only
omap2_clk_prepare_for_reboot() is only applicable to OMAP2xxx chips, so rename it to omap2xxx_clk_prepare_for_reboot() and only call it when running on OMAP2xxx chips. Remove the old stub in the OMAP3 clock code. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.c')
-rw-r--r--arch/arm/mach-omap2/clock34xx.c21
1 files changed, 2 insertions, 19 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 8a7db7a03bec..34d395046280 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -150,25 +150,6 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
150 return omap3_noncore_dpll_set_rate(clk, rate); 150 return omap3_noncore_dpll_set_rate(clk, rate);
151} 151}
152 152
153/* Common clock code */
154
155/*
156 * Set clocks for bypass mode for reboot to work.
157 */
158void omap2_clk_prepare_for_reboot(void)
159{
160 /* REVISIT: Not ready for 343x */
161#if 0
162 u32 rate;
163
164 if (vclk == NULL || sclk == NULL)
165 return;
166
167 rate = clk_get_rate(sclk);
168 clk_set_rate(vclk, rate);
169#endif
170}
171
172void omap3_clk_lock_dpll5(void) 153void omap3_clk_lock_dpll5(void)
173{ 154{
174 struct clk *dpll5_clk; 155 struct clk *dpll5_clk;
@@ -191,6 +172,8 @@ void omap3_clk_lock_dpll5(void)
191 return; 172 return;
192} 173}
193 174
175/* Common clock code */
176
194/* REVISIT: Move this init stuff out into clock.c */ 177/* REVISIT: Move this init stuff out into clock.c */
195 178
196/* 179/*