diff options
author | Paul Walmsley <paul@pwsan.com> | 2009-05-12 19:26:32 -0400 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-05-12 19:27:10 -0400 |
commit | 4519c2bf433b97d091635eb51e4ba8ffa1c84d62 (patch) | |
tree | 0b36fc5e39c6a29005783c74f727c953c75e2198 /arch/arm/mach-omap2/clock34xx.c | |
parent | b2abb271a5705bc80478e79d95fc9f3babc2605c (diff) |
OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz
According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz. CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations. Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.c')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 0a14dca31e30..811360af60dc 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -281,6 +281,8 @@ static struct omap_clk omap34xx_clks[] = { | |||
281 | 281 | ||
282 | #define MAX_DPLL_WAIT_TRIES 1000000 | 282 | #define MAX_DPLL_WAIT_TRIES 1000000 |
283 | 283 | ||
284 | #define MIN_SDRC_DLL_LOCK_FREQ 83000000 | ||
285 | |||
284 | /** | 286 | /** |
285 | * omap3_dpll_recalc - recalculate DPLL rate | 287 | * omap3_dpll_recalc - recalculate DPLL rate |
286 | * @clk: DPLL struct clk | 288 | * @clk: DPLL struct clk |
@@ -703,6 +705,7 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | |||
703 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | 705 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) |
704 | { | 706 | { |
705 | u32 new_div = 0; | 707 | u32 new_div = 0; |
708 | u32 unlock_dll = 0; | ||
706 | unsigned long validrate, sdrcrate; | 709 | unsigned long validrate, sdrcrate; |
707 | struct omap_sdrc_params *sp; | 710 | struct omap_sdrc_params *sp; |
708 | 711 | ||
@@ -729,6 +732,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
729 | if (!sp) | 732 | if (!sp) |
730 | return -EINVAL; | 733 | return -EINVAL; |
731 | 734 | ||
735 | if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { | ||
736 | pr_debug("clock: will unlock SDRC DLL\n"); | ||
737 | unlock_dll = 1; | ||
738 | } | ||
739 | |||
732 | pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | 740 | pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, |
733 | validrate); | 741 | validrate); |
734 | pr_info("clock: SDRC timing params used: %08x %08x %08x\n", | 742 | pr_info("clock: SDRC timing params used: %08x %08x %08x\n", |
@@ -739,7 +747,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
739 | 747 | ||
740 | /* REVISIT: Add SDRC_MR changing to this code also */ | 748 | /* REVISIT: Add SDRC_MR changing to this code also */ |
741 | omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, | 749 | omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, |
742 | sp->actim_ctrlb, new_div); | 750 | sp->actim_ctrlb, new_div, unlock_dll); |
743 | 751 | ||
744 | return 0; | 752 | return 0; |
745 | } | 753 | } |