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authorPaul Walmsley <paul@pwsan.com>2010-02-23 00:09:19 -0500
committerPaul Walmsley <paul@pwsan.com>2010-02-24 14:16:13 -0500
commitb92c170d019db7554db95380d2e1dfb3a368e350 (patch)
tree2ab2743375335d56683b83cea48876eb37a43b81 /arch/arm/mach-omap2/clock2xxx_data.c
parentf71eddb1582f5c53ed4bfc365a2acce94aca88cc (diff)
OMAP clock: drop .id field; ensure each clock has a unique name
After the clkdev conversion, the struct clk.id field became superfluous, so, drop it. Bring the clock names closer to the TRMs and ensure they are unique for debugfs. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock2xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock2xxx_data.c81
1 files changed, 28 insertions, 53 deletions
diff --git a/arch/arm/mach-omap2/clock2xxx_data.c b/arch/arm/mach-omap2/clock2xxx_data.c
index 9bcef44fb140..82ad8b439eb9 100644
--- a/arch/arm/mach-omap2/clock2xxx_data.c
+++ b/arch/arm/mach-omap2/clock2xxx_data.c
@@ -1224,9 +1224,8 @@ static struct clk gpt12_fck = {
1224}; 1224};
1225 1225
1226static struct clk mcbsp1_ick = { 1226static struct clk mcbsp1_ick = {
1227 .name = "mcbsp_ick", 1227 .name = "mcbsp1_ick",
1228 .ops = &clkops_omap2_dflt_wait, 1228 .ops = &clkops_omap2_dflt_wait,
1229 .id = 1,
1230 .parent = &l4_ck, 1229 .parent = &l4_ck,
1231 .clkdm_name = "core_l4_clkdm", 1230 .clkdm_name = "core_l4_clkdm",
1232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1231 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1235,9 +1234,8 @@ static struct clk mcbsp1_ick = {
1235}; 1234};
1236 1235
1237static struct clk mcbsp1_fck = { 1236static struct clk mcbsp1_fck = {
1238 .name = "mcbsp_fck", 1237 .name = "mcbsp1_fck",
1239 .ops = &clkops_omap2_dflt_wait, 1238 .ops = &clkops_omap2_dflt_wait,
1240 .id = 1,
1241 .parent = &func_96m_ck, 1239 .parent = &func_96m_ck,
1242 .clkdm_name = "core_l4_clkdm", 1240 .clkdm_name = "core_l4_clkdm",
1243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1241 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1246,9 +1244,8 @@ static struct clk mcbsp1_fck = {
1246}; 1244};
1247 1245
1248static struct clk mcbsp2_ick = { 1246static struct clk mcbsp2_ick = {
1249 .name = "mcbsp_ick", 1247 .name = "mcbsp2_ick",
1250 .ops = &clkops_omap2_dflt_wait, 1248 .ops = &clkops_omap2_dflt_wait,
1251 .id = 2,
1252 .parent = &l4_ck, 1249 .parent = &l4_ck,
1253 .clkdm_name = "core_l4_clkdm", 1250 .clkdm_name = "core_l4_clkdm",
1254 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1251 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1257,9 +1254,8 @@ static struct clk mcbsp2_ick = {
1257}; 1254};
1258 1255
1259static struct clk mcbsp2_fck = { 1256static struct clk mcbsp2_fck = {
1260 .name = "mcbsp_fck", 1257 .name = "mcbsp2_fck",
1261 .ops = &clkops_omap2_dflt_wait, 1258 .ops = &clkops_omap2_dflt_wait,
1262 .id = 2,
1263 .parent = &func_96m_ck, 1259 .parent = &func_96m_ck,
1264 .clkdm_name = "core_l4_clkdm", 1260 .clkdm_name = "core_l4_clkdm",
1265 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1261 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1268,9 +1264,8 @@ static struct clk mcbsp2_fck = {
1268}; 1264};
1269 1265
1270static struct clk mcbsp3_ick = { 1266static struct clk mcbsp3_ick = {
1271 .name = "mcbsp_ick", 1267 .name = "mcbsp3_ick",
1272 .ops = &clkops_omap2_dflt_wait, 1268 .ops = &clkops_omap2_dflt_wait,
1273 .id = 3,
1274 .parent = &l4_ck, 1269 .parent = &l4_ck,
1275 .clkdm_name = "core_l4_clkdm", 1270 .clkdm_name = "core_l4_clkdm",
1276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1271 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1279,9 +1274,8 @@ static struct clk mcbsp3_ick = {
1279}; 1274};
1280 1275
1281static struct clk mcbsp3_fck = { 1276static struct clk mcbsp3_fck = {
1282 .name = "mcbsp_fck", 1277 .name = "mcbsp3_fck",
1283 .ops = &clkops_omap2_dflt_wait, 1278 .ops = &clkops_omap2_dflt_wait,
1284 .id = 3,
1285 .parent = &func_96m_ck, 1279 .parent = &func_96m_ck,
1286 .clkdm_name = "core_l4_clkdm", 1280 .clkdm_name = "core_l4_clkdm",
1287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1281 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1290,9 +1284,8 @@ static struct clk mcbsp3_fck = {
1290}; 1284};
1291 1285
1292static struct clk mcbsp4_ick = { 1286static struct clk mcbsp4_ick = {
1293 .name = "mcbsp_ick", 1287 .name = "mcbsp4_ick",
1294 .ops = &clkops_omap2_dflt_wait, 1288 .ops = &clkops_omap2_dflt_wait,
1295 .id = 4,
1296 .parent = &l4_ck, 1289 .parent = &l4_ck,
1297 .clkdm_name = "core_l4_clkdm", 1290 .clkdm_name = "core_l4_clkdm",
1298 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1301,9 +1294,8 @@ static struct clk mcbsp4_ick = {
1301}; 1294};
1302 1295
1303static struct clk mcbsp4_fck = { 1296static struct clk mcbsp4_fck = {
1304 .name = "mcbsp_fck", 1297 .name = "mcbsp4_fck",
1305 .ops = &clkops_omap2_dflt_wait, 1298 .ops = &clkops_omap2_dflt_wait,
1306 .id = 4,
1307 .parent = &func_96m_ck, 1299 .parent = &func_96m_ck,
1308 .clkdm_name = "core_l4_clkdm", 1300 .clkdm_name = "core_l4_clkdm",
1309 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1301 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1312,9 +1304,8 @@ static struct clk mcbsp4_fck = {
1312}; 1304};
1313 1305
1314static struct clk mcbsp5_ick = { 1306static struct clk mcbsp5_ick = {
1315 .name = "mcbsp_ick", 1307 .name = "mcbsp5_ick",
1316 .ops = &clkops_omap2_dflt_wait, 1308 .ops = &clkops_omap2_dflt_wait,
1317 .id = 5,
1318 .parent = &l4_ck, 1309 .parent = &l4_ck,
1319 .clkdm_name = "core_l4_clkdm", 1310 .clkdm_name = "core_l4_clkdm",
1320 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1323,9 +1314,8 @@ static struct clk mcbsp5_ick = {
1323}; 1314};
1324 1315
1325static struct clk mcbsp5_fck = { 1316static struct clk mcbsp5_fck = {
1326 .name = "mcbsp_fck", 1317 .name = "mcbsp5_fck",
1327 .ops = &clkops_omap2_dflt_wait, 1318 .ops = &clkops_omap2_dflt_wait,
1328 .id = 5,
1329 .parent = &func_96m_ck, 1319 .parent = &func_96m_ck,
1330 .clkdm_name = "core_l4_clkdm", 1320 .clkdm_name = "core_l4_clkdm",
1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1321 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1334,9 +1324,8 @@ static struct clk mcbsp5_fck = {
1334}; 1324};
1335 1325
1336static struct clk mcspi1_ick = { 1326static struct clk mcspi1_ick = {
1337 .name = "mcspi_ick", 1327 .name = "mcspi1_ick",
1338 .ops = &clkops_omap2_dflt_wait, 1328 .ops = &clkops_omap2_dflt_wait,
1339 .id = 1,
1340 .parent = &l4_ck, 1329 .parent = &l4_ck,
1341 .clkdm_name = "core_l4_clkdm", 1330 .clkdm_name = "core_l4_clkdm",
1342 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1345,9 +1334,8 @@ static struct clk mcspi1_ick = {
1345}; 1334};
1346 1335
1347static struct clk mcspi1_fck = { 1336static struct clk mcspi1_fck = {
1348 .name = "mcspi_fck", 1337 .name = "mcspi1_fck",
1349 .ops = &clkops_omap2_dflt_wait, 1338 .ops = &clkops_omap2_dflt_wait,
1350 .id = 1,
1351 .parent = &func_48m_ck, 1339 .parent = &func_48m_ck,
1352 .clkdm_name = "core_l4_clkdm", 1340 .clkdm_name = "core_l4_clkdm",
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1356,9 +1344,8 @@ static struct clk mcspi1_fck = {
1356}; 1344};
1357 1345
1358static struct clk mcspi2_ick = { 1346static struct clk mcspi2_ick = {
1359 .name = "mcspi_ick", 1347 .name = "mcspi2_ick",
1360 .ops = &clkops_omap2_dflt_wait, 1348 .ops = &clkops_omap2_dflt_wait,
1361 .id = 2,
1362 .parent = &l4_ck, 1349 .parent = &l4_ck,
1363 .clkdm_name = "core_l4_clkdm", 1350 .clkdm_name = "core_l4_clkdm",
1364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1367,9 +1354,8 @@ static struct clk mcspi2_ick = {
1367}; 1354};
1368 1355
1369static struct clk mcspi2_fck = { 1356static struct clk mcspi2_fck = {
1370 .name = "mcspi_fck", 1357 .name = "mcspi2_fck",
1371 .ops = &clkops_omap2_dflt_wait, 1358 .ops = &clkops_omap2_dflt_wait,
1372 .id = 2,
1373 .parent = &func_48m_ck, 1359 .parent = &func_48m_ck,
1374 .clkdm_name = "core_l4_clkdm", 1360 .clkdm_name = "core_l4_clkdm",
1375 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1361 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1378,9 +1364,8 @@ static struct clk mcspi2_fck = {
1378}; 1364};
1379 1365
1380static struct clk mcspi3_ick = { 1366static struct clk mcspi3_ick = {
1381 .name = "mcspi_ick", 1367 .name = "mcspi3_ick",
1382 .ops = &clkops_omap2_dflt_wait, 1368 .ops = &clkops_omap2_dflt_wait,
1383 .id = 3,
1384 .parent = &l4_ck, 1369 .parent = &l4_ck,
1385 .clkdm_name = "core_l4_clkdm", 1370 .clkdm_name = "core_l4_clkdm",
1386 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1389,9 +1374,8 @@ static struct clk mcspi3_ick = {
1389}; 1374};
1390 1375
1391static struct clk mcspi3_fck = { 1376static struct clk mcspi3_fck = {
1392 .name = "mcspi_fck", 1377 .name = "mcspi3_fck",
1393 .ops = &clkops_omap2_dflt_wait, 1378 .ops = &clkops_omap2_dflt_wait,
1394 .id = 3,
1395 .parent = &func_48m_ck, 1379 .parent = &func_48m_ck,
1396 .clkdm_name = "core_l4_clkdm", 1380 .clkdm_name = "core_l4_clkdm",
1397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1381 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1717,9 +1701,8 @@ static struct clk hdq_fck = {
1717}; 1701};
1718 1702
1719static struct clk i2c2_ick = { 1703static struct clk i2c2_ick = {
1720 .name = "i2c_ick", 1704 .name = "i2c2_ick",
1721 .ops = &clkops_omap2_dflt_wait, 1705 .ops = &clkops_omap2_dflt_wait,
1722 .id = 2,
1723 .parent = &l4_ck, 1706 .parent = &l4_ck,
1724 .clkdm_name = "core_l4_clkdm", 1707 .clkdm_name = "core_l4_clkdm",
1725 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1708 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1728,9 +1711,8 @@ static struct clk i2c2_ick = {
1728}; 1711};
1729 1712
1730static struct clk i2c2_fck = { 1713static struct clk i2c2_fck = {
1731 .name = "i2c_fck", 1714 .name = "i2c2_fck",
1732 .ops = &clkops_omap2_dflt_wait, 1715 .ops = &clkops_omap2_dflt_wait,
1733 .id = 2,
1734 .parent = &func_12m_ck, 1716 .parent = &func_12m_ck,
1735 .clkdm_name = "core_l4_clkdm", 1717 .clkdm_name = "core_l4_clkdm",
1736 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1739,9 +1721,8 @@ static struct clk i2c2_fck = {
1739}; 1721};
1740 1722
1741static struct clk i2chs2_fck = { 1723static struct clk i2chs2_fck = {
1742 .name = "i2c_fck", 1724 .name = "i2chs2_fck",
1743 .ops = &clkops_omap2430_i2chs_wait, 1725 .ops = &clkops_omap2430_i2chs_wait,
1744 .id = 2,
1745 .parent = &func_96m_ck, 1726 .parent = &func_96m_ck,
1746 .clkdm_name = "core_l4_clkdm", 1727 .clkdm_name = "core_l4_clkdm",
1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1728 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1750,9 +1731,8 @@ static struct clk i2chs2_fck = {
1750}; 1731};
1751 1732
1752static struct clk i2c1_ick = { 1733static struct clk i2c1_ick = {
1753 .name = "i2c_ick", 1734 .name = "i2c1_ick",
1754 .ops = &clkops_omap2_dflt_wait, 1735 .ops = &clkops_omap2_dflt_wait,
1755 .id = 1,
1756 .parent = &l4_ck, 1736 .parent = &l4_ck,
1757 .clkdm_name = "core_l4_clkdm", 1737 .clkdm_name = "core_l4_clkdm",
1758 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1761,9 +1741,8 @@ static struct clk i2c1_ick = {
1761}; 1741};
1762 1742
1763static struct clk i2c1_fck = { 1743static struct clk i2c1_fck = {
1764 .name = "i2c_fck", 1744 .name = "i2c1_fck",
1765 .ops = &clkops_omap2_dflt_wait, 1745 .ops = &clkops_omap2_dflt_wait,
1766 .id = 1,
1767 .parent = &func_12m_ck, 1746 .parent = &func_12m_ck,
1768 .clkdm_name = "core_l4_clkdm", 1747 .clkdm_name = "core_l4_clkdm",
1769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1748 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1772,9 +1751,8 @@ static struct clk i2c1_fck = {
1772}; 1751};
1773 1752
1774static struct clk i2chs1_fck = { 1753static struct clk i2chs1_fck = {
1775 .name = "i2c_fck", 1754 .name = "i2chs1_fck",
1776 .ops = &clkops_omap2430_i2chs_wait, 1755 .ops = &clkops_omap2430_i2chs_wait,
1777 .id = 1,
1778 .parent = &func_96m_ck, 1756 .parent = &func_96m_ck,
1779 .clkdm_name = "core_l4_clkdm", 1757 .clkdm_name = "core_l4_clkdm",
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1758 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1941,7 +1919,7 @@ static struct clk usbhs_ick = {
1941}; 1919};
1942 1920
1943static struct clk mmchs1_ick = { 1921static struct clk mmchs1_ick = {
1944 .name = "mmchs_ick", 1922 .name = "mmchs1_ick",
1945 .ops = &clkops_omap2_dflt_wait, 1923 .ops = &clkops_omap2_dflt_wait,
1946 .parent = &l4_ck, 1924 .parent = &l4_ck,
1947 .clkdm_name = "core_l4_clkdm", 1925 .clkdm_name = "core_l4_clkdm",
@@ -1951,7 +1929,7 @@ static struct clk mmchs1_ick = {
1951}; 1929};
1952 1930
1953static struct clk mmchs1_fck = { 1931static struct clk mmchs1_fck = {
1954 .name = "mmchs_fck", 1932 .name = "mmchs1_fck",
1955 .ops = &clkops_omap2_dflt_wait, 1933 .ops = &clkops_omap2_dflt_wait,
1956 .parent = &func_96m_ck, 1934 .parent = &func_96m_ck,
1957 .clkdm_name = "core_l3_clkdm", 1935 .clkdm_name = "core_l3_clkdm",
@@ -1961,9 +1939,8 @@ static struct clk mmchs1_fck = {
1961}; 1939};
1962 1940
1963static struct clk mmchs2_ick = { 1941static struct clk mmchs2_ick = {
1964 .name = "mmchs_ick", 1942 .name = "mmchs2_ick",
1965 .ops = &clkops_omap2_dflt_wait, 1943 .ops = &clkops_omap2_dflt_wait,
1966 .id = 1,
1967 .parent = &l4_ck, 1944 .parent = &l4_ck,
1968 .clkdm_name = "core_l4_clkdm", 1945 .clkdm_name = "core_l4_clkdm",
1969 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1972,9 +1949,8 @@ static struct clk mmchs2_ick = {
1972}; 1949};
1973 1950
1974static struct clk mmchs2_fck = { 1951static struct clk mmchs2_fck = {
1975 .name = "mmchs_fck", 1952 .name = "mmchs2_fck",
1976 .ops = &clkops_omap2_dflt_wait, 1953 .ops = &clkops_omap2_dflt_wait,
1977 .id = 1,
1978 .parent = &func_96m_ck, 1954 .parent = &func_96m_ck,
1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1955 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1980 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 1956 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
@@ -2012,7 +1988,7 @@ static struct clk mdm_intc_ick = {
2012}; 1988};
2013 1989
2014static struct clk mmchsdb1_fck = { 1990static struct clk mmchsdb1_fck = {
2015 .name = "mmchsdb_fck", 1991 .name = "mmchsdb1_fck",
2016 .ops = &clkops_omap2_dflt_wait, 1992 .ops = &clkops_omap2_dflt_wait,
2017 .parent = &func_32k_ck, 1993 .parent = &func_32k_ck,
2018 .clkdm_name = "core_l4_clkdm", 1994 .clkdm_name = "core_l4_clkdm",
@@ -2022,9 +1998,8 @@ static struct clk mmchsdb1_fck = {
2022}; 1998};
2023 1999
2024static struct clk mmchsdb2_fck = { 2000static struct clk mmchsdb2_fck = {
2025 .name = "mmchsdb_fck", 2001 .name = "mmchsdb2_fck",
2026 .ops = &clkops_omap2_dflt_wait, 2002 .ops = &clkops_omap2_dflt_wait,
2027 .id = 1,
2028 .parent = &func_32k_ck, 2003 .parent = &func_32k_ck,
2029 .clkdm_name = "core_l4_clkdm", 2004 .clkdm_name = "core_l4_clkdm",
2030 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2005 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),