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authorPaul Walmsley <paul@pwsan.com>2010-02-23 00:09:36 -0500
committerPaul Walmsley <paul@pwsan.com>2010-02-24 19:45:15 -0500
commit4d30e82c26b7212021b9a5ab57760d9b8a3075fe (patch)
treeb824e735401ccf62eb762db68d06c4bd3231fab5 /arch/arm/mach-omap2/clock2xxx.c
parentad9561609c41f704fd82facd37127e957bcaea94 (diff)
OMAP2/3 clock: combine OMAP2 & 3 boot-time MPU rate change code
The OMAP2 and OMAP3 boot-time MPU rate change code is almost identical. Merge them into mach-omap2/clock.c, and add kerneldoc documentation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock2xxx.c')
-rw-r--r--arch/arm/mach-omap2/clock2xxx.c34
1 files changed, 9 insertions, 25 deletions
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 7a2f5ad07bab..80bb0f0e92e6 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -50,40 +50,24 @@ void omap2xxx_clk_prepare_for_reboot(void)
50} 50}
51 51
52/* 52/*
53 * Switch the MPU rate if specified on cmdline. 53 * Switch the MPU rate if specified on cmdline. We cannot do this
54 * We cannot do this early until cmdline is parsed. 54 * early until cmdline is parsed. XXX This should be removed from the
55 * clock code and handled by the OPP layer code in the near future.
55 */ 56 */
56static int __init omap2xxx_clk_arch_init(void) 57static int __init omap2xxx_clk_arch_init(void)
57{ 58{
58 struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck; 59 int ret;
59 unsigned long sys_ck_rate;
60 60
61 if (!cpu_is_omap24xx()) 61 if (!cpu_is_omap24xx())
62 return 0; 62 return 0;
63 63
64 if (!mpurate) 64 ret = omap2_clk_switch_mpurate_at_boot("virt_prcm_set");
65 return -EINVAL; 65 if (!ret)
66 omap2_clk_print_new_rates("sys_ck", "dpll_ck", "mpu_ck");
66 67
67 virt_prcm_set = clk_get(NULL, "virt_prcm_set"); 68 return ret;
68 sys_ck = clk_get(NULL, "sys_ck");
69 dpll_ck = clk_get(NULL, "dpll_ck");
70 mpu_ck = clk_get(NULL, "mpu_ck");
71
72 if (clk_set_rate(virt_prcm_set, mpurate))
73 pr_err("Could not find matching MPU rate\n");
74
75 recalculate_root_clocks();
76
77 sys_ck_rate = clk_get_rate(sys_ck);
78
79 pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
80 "%ld.%01ld/%ld/%ld MHz\n",
81 (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
82 (clk_get_rate(dpll_ck) / 1000000),
83 (clk_get_rate(mpu_ck) / 1000000));
84
85 return 0;
86} 69}
70
87arch_initcall(omap2xxx_clk_arch_init); 71arch_initcall(omap2xxx_clk_arch_init);
88 72
89 73