aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/clock24xx.h
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-11-04 09:02:46 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-02 09:52:18 -0500
commit548d849574847b788fe846fe21a41386063be161 (patch)
tree6c2ac7379c376793368affab03e5202abd0f1efa /arch/arm/mach-omap2/clock24xx.h
parentdb8ac47cfccaafd3fa4c5c15320809d44f4fcef9 (diff)
[ARM] omap: introduce clock operations structure
Collect up all the common enable/disable clock operation functions into a separate operations structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock24xx.h')
-rw-r--r--arch/arm/mach-omap2/clock24xx.h13
1 files changed, 3 insertions, 10 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 8c57a2e180f6..2aa0b5e65608 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -31,10 +31,6 @@ static void omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk); 31static void omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk); 32static void omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpllcore_recalc(struct clk *clk); 33static void omap2_dpllcore_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); 34static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
39 35
40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 36/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
@@ -633,11 +629,10 @@ static struct clk func_32k_ck = {
633/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ 629/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ 630static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
635 .name = "osc_ck", 631 .name = "osc_ck",
632 .ops = &clkops_oscck,
636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 633 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
637 RATE_PROPAGATES, 634 RATE_PROPAGATES,
638 .clkdm_name = "wkup_clkdm", 635 .clkdm_name = "wkup_clkdm",
639 .enable = &omap2_enable_osc_ck,
640 .disable = &omap2_disable_osc_ck,
641 .recalc = &omap2_osc_clk_recalc, 636 .recalc = &omap2_osc_clk_recalc,
642}; 637};
643 638
@@ -695,6 +690,7 @@ static struct clk dpll_ck = {
695 690
696static struct clk apll96_ck = { 691static struct clk apll96_ck = {
697 .name = "apll96_ck", 692 .name = "apll96_ck",
693 .ops = &clkops_fixed,
698 .parent = &sys_ck, 694 .parent = &sys_ck,
699 .rate = 96000000, 695 .rate = 96000000,
700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 696 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
@@ -702,13 +698,12 @@ static struct clk apll96_ck = {
702 .clkdm_name = "wkup_clkdm", 698 .clkdm_name = "wkup_clkdm",
703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 699 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 700 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
705 .enable = &omap2_clk_fixed_enable,
706 .disable = &omap2_clk_fixed_disable,
707 .recalc = &propagate_rate, 701 .recalc = &propagate_rate,
708}; 702};
709 703
710static struct clk apll54_ck = { 704static struct clk apll54_ck = {
711 .name = "apll54_ck", 705 .name = "apll54_ck",
706 .ops = &clkops_fixed,
712 .parent = &sys_ck, 707 .parent = &sys_ck,
713 .rate = 54000000, 708 .rate = 54000000,
714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 709 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
@@ -716,8 +711,6 @@ static struct clk apll54_ck = {
716 .clkdm_name = "wkup_clkdm", 711 .clkdm_name = "wkup_clkdm",
717 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 712 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
718 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 713 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
719 .enable = &omap2_clk_fixed_enable,
720 .disable = &omap2_clk_fixed_disable,
721 .recalc = &propagate_rate, 714 .recalc = &propagate_rate,
722}; 715};
723 716