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authorPaul Walmsley <paul@pwsan.com>2008-03-18 09:47:55 -0400
committerTony Lindgren <tony@atomide.com>2008-04-14 13:29:38 -0400
commite32744b02d2d8f5242720998c9f955d8545751ac (patch)
treeba2dc1cd176932c95bc7ffe71d9d44701e725d97 /arch/arm/mach-omap2/clock24xx.h
parent6b8858a972a0eff1dc1ab77b0fd9fc25387c217c (diff)
ARM: OMAP: Add rest of 24xx clocks
This patch adds the rest of clocks for 24xx. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock24xx.h')
-rw-r--r--arch/arm/mach-omap2/clock24xx.h1487
1 files changed, 957 insertions, 530 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 9363c207f581..ccf6a6ca5ce4 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -621,41 +621,42 @@ static struct prcm_config rate_table[] = {
621 * clocks. 621 * clocks.
622 *-------------------------------------------------------------------------*/ 622 *-------------------------------------------------------------------------*/
623 623
624#ifdef OLD_CK
625/* Base external input clocks */ 624/* Base external input clocks */
626static struct clk func_32k_ck = { 625static struct clk func_32k_ck = {
627 .name = "func_32k_ck", 626 .name = "func_32k_ck",
628 .rate = 32000, 627 .rate = 32000,
629 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 628 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
630 RATE_FIXED | ALWAYS_ENABLED, 629 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
630 .recalc = &propagate_rate,
631}; 631};
632#endif /* OLD_CK */ 632
633/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ 633/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ 634static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
635 .name = "osc_ck", 635 .name = "osc_ck",
636 .rate = 26000000, /* fixed up in clock init */
637 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
638 RATE_FIXED | RATE_PROPAGATES, 637 RATE_PROPAGATES,
638 .enable = &omap2_enable_osc_ck,
639 .disable = &omap2_disable_osc_ck,
640 .recalc = &omap2_osc_clk_recalc,
639}; 641};
640 642
641/* With out modem likely 12MHz, with modem likely 13MHz */ 643/* With out modem likely 12MHz, with modem likely 13MHz */
642static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ 644static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
643 .name = "sys_ck", /* ~ ref_clk also */ 645 .name = "sys_ck", /* ~ ref_clk also */
644 .parent = &osc_ck, 646 .parent = &osc_ck,
645 .rate = 13000000,
646 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 647 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
647 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 648 ALWAYS_ENABLED | RATE_PROPAGATES,
648 .recalc = &omap2_sys_clk_recalc, 649 .recalc = &omap2_sys_clk_recalc,
649}; 650};
650#ifdef OLD_CK 651
651static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ 652static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
652 .name = "alt_ck", 653 .name = "alt_ck",
653 .rate = 54000000, 654 .rate = 54000000,
654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 655 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
655 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 656 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
656 .recalc = &omap2_propagate_rate, 657 .recalc = &propagate_rate,
657}; 658};
658#endif /* OLD_CK */ 659
659/* 660/*
660 * Analog domain root source clocks 661 * Analog domain root source clocks
661 */ 662 */
@@ -710,19 +711,37 @@ static struct clk apll54_ck = {
710/* 711/*
711 * PRCM digital base sources 712 * PRCM digital base sources
712 */ 713 */
713#ifdef OLD_CK 714
715/* func_54m_ck */
716
717static const struct clksel_rate func_54m_apll54_rates[] = {
718 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
719 { .div = 0 },
720};
721
722static const struct clksel_rate func_54m_alt_rates[] = {
723 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
724 { .div = 0 },
725};
726
727static const struct clksel func_54m_clksel[] = {
728 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
729 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
730 { .parent = NULL },
731};
732
714static struct clk func_54m_ck = { 733static struct clk func_54m_ck = {
715 .name = "func_54m_ck", 734 .name = "func_54m_ck",
716 .parent = &apll54_ck, /* can also be alt_clk */ 735 .parent = &apll54_ck, /* can also be alt_clk */
717 .rate = 54000000,
718 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 736 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
719 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES, 737 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
720 .src_offset = 5, 738 .init = &omap2_init_clksel_parent,
721 .enable_reg = (void __iomem *)&CM_CLKEN_PLL, 739 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
722 .enable_bit = 0xff, 740 .clksel_mask = OMAP24XX_54M_SOURCE,
723 .recalc = &omap2_propagate_rate, 741 .clksel = func_54m_clksel,
742 .recalc = &omap2_clksel_recalc,
724}; 743};
725#endif /* OLD_CK */ 744
726static struct clk core_ck = { 745static struct clk core_ck = {
727 .name = "core_ck", 746 .name = "core_ck",
728 .parent = &dpll_ck, /* can also be 32k */ 747 .parent = &dpll_ck, /* can also be 32k */
@@ -730,47 +749,78 @@ static struct clk core_ck = {
730 ALWAYS_ENABLED | RATE_PROPAGATES, 749 ALWAYS_ENABLED | RATE_PROPAGATES,
731 .recalc = &followparent_recalc, 750 .recalc = &followparent_recalc,
732}; 751};
733#ifdef OLD_CK 752
734static struct clk sleep_ck = { /* sys_clk or 32k */ 753/* func_96m_ck */
735 .name = "sleep_ck", 754static const struct clksel_rate func_96m_apll96_rates[] = {
736 .parent = &func_32k_ck, 755 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
737 .rate = 32000, 756 { .div = 0 },
738 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
739 .recalc = &omap2_propagate_rate,
740}; 757};
741 758
759static const struct clksel_rate func_96m_alt_rates[] = {
760 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
761 { .div = 0 },
762};
763
764static const struct clksel func_96m_clksel[] = {
765 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
766 { .parent = &alt_ck, .rates = func_96m_alt_rates },
767 { .parent = NULL }
768};
769
770/* The parent of this clock is not selectable on 2420. */
742static struct clk func_96m_ck = { 771static struct clk func_96m_ck = {
743 .name = "func_96m_ck", 772 .name = "func_96m_ck",
744 .parent = &apll96_ck, 773 .parent = &apll96_ck,
745 .rate = 96000000,
746 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 774 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
747 RATE_FIXED | RATE_PROPAGATES, 775 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
748 .enable_reg = (void __iomem *)&CM_CLKEN_PLL, 776 .init = &omap2_init_clksel_parent,
749 .enable_bit = 0xff, 777 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
750 .recalc = &omap2_propagate_rate, 778 .clksel_mask = OMAP2430_96M_SOURCE,
779 .clksel = func_96m_clksel,
780 .recalc = &omap2_clksel_recalc,
781 .round_rate = &omap2_clksel_round_rate,
782 .set_rate = &omap2_clksel_set_rate
783};
784
785/* func_48m_ck */
786
787static const struct clksel_rate func_48m_apll96_rates[] = {
788 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
789 { .div = 0 },
790};
791
792static const struct clksel_rate func_48m_alt_rates[] = {
793 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
794 { .div = 0 },
795};
796
797static const struct clksel func_48m_clksel[] = {
798 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
799 { .parent = &alt_ck, .rates = func_48m_alt_rates },
800 { .parent = NULL }
751}; 801};
752 802
753static struct clk func_48m_ck = { 803static struct clk func_48m_ck = {
754 .name = "func_48m_ck", 804 .name = "func_48m_ck",
755 .parent = &apll96_ck, /* 96M or Alt */ 805 .parent = &apll96_ck, /* 96M or Alt */
756 .rate = 48000000,
757 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 806 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
758 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES, 807 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
759 .src_offset = 3, 808 .init = &omap2_init_clksel_parent,
760 .enable_reg = (void __iomem *)&CM_CLKEN_PLL, 809 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
761 .enable_bit = 0xff, 810 .clksel_mask = OMAP24XX_48M_SOURCE,
762 .recalc = &omap2_propagate_rate, 811 .clksel = func_48m_clksel,
812 .recalc = &omap2_clksel_recalc,
813 .round_rate = &omap2_clksel_round_rate,
814 .set_rate = &omap2_clksel_set_rate
763}; 815};
764 816
765static struct clk func_12m_ck = { 817static struct clk func_12m_ck = {
766 .name = "func_12m_ck", 818 .name = "func_12m_ck",
767 .parent = &func_48m_ck, 819 .parent = &func_48m_ck,
768 .rate = 12000000, 820 .fixed_div = 4,
769 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 821 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
770 RATE_FIXED | RATE_PROPAGATES, 822 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
771 .recalc = &omap2_propagate_rate, 823 .recalc = &omap2_fixed_divisor_recalc,
772 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
773 .enable_bit = 0xff,
774}; 824};
775 825
776/* Secure timer, only available in secure mode */ 826/* Secure timer, only available in secure mode */
@@ -778,46 +828,132 @@ static struct clk wdt1_osc_ck = {
778 .name = "ck_wdt1_osc", 828 .name = "ck_wdt1_osc",
779 .parent = &osc_ck, 829 .parent = &osc_ck,
780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 830 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
781 .recalc = &omap2_followparent_recalc, 831 .recalc = &followparent_recalc,
832};
833
834/*
835 * The common_clkout* clksel_rate structs are common to
836 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
837 * sys_clkout2_* are 2420-only, so the
838 * clksel_rate flags fields are inaccurate for those clocks. This is
839 * harmless since access to those clocks are gated by the struct clk
840 * flags fields, which mark them as 2420-only.
841 */
842static const struct clksel_rate common_clkout_src_core_rates[] = {
843 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
844 { .div = 0 }
845};
846
847static const struct clksel_rate common_clkout_src_sys_rates[] = {
848 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
849 { .div = 0 }
850};
851
852static const struct clksel_rate common_clkout_src_96m_rates[] = {
853 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
854 { .div = 0 }
855};
856
857static const struct clksel_rate common_clkout_src_54m_rates[] = {
858 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
859 { .div = 0 }
860};
861
862static const struct clksel common_clkout_src_clksel[] = {
863 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
864 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
865 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
866 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
867 { .parent = NULL }
868};
869
870static struct clk sys_clkout_src = {
871 .name = "sys_clkout_src",
872 .parent = &func_54m_ck,
873 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
874 RATE_PROPAGATES,
875 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
876 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
877 .init = &omap2_init_clksel_parent,
878 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
879 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
880 .clksel = common_clkout_src_clksel,
881 .recalc = &omap2_clksel_recalc,
882 .round_rate = &omap2_clksel_round_rate,
883 .set_rate = &omap2_clksel_set_rate
884};
885
886static const struct clksel_rate common_clkout_rates[] = {
887 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
888 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
889 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
890 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
891 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
892 { .div = 0 },
893};
894
895static const struct clksel sys_clkout_clksel[] = {
896 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
897 { .parent = NULL }
782}; 898};
783 899
784static struct clk sys_clkout = { 900static struct clk sys_clkout = {
785 .name = "sys_clkout", 901 .name = "sys_clkout",
786 .parent = &func_54m_ck, 902 .parent = &sys_clkout_src,
787 .rate = 54000000,
788 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 903 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
789 CM_SYSCLKOUT_SEL1 | RATE_CKCTL, 904 PARENT_CONTROLS_CLOCK,
790 .src_offset = 0, 905 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
791 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL, 906 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
792 .enable_bit = 7, 907 .clksel = sys_clkout_clksel,
793 .rate_offset = 3, 908 .recalc = &omap2_clksel_recalc,
909 .round_rate = &omap2_clksel_round_rate,
910 .set_rate = &omap2_clksel_set_rate
911};
912
913/* In 2430, new in 2420 ES2 */
914static struct clk sys_clkout2_src = {
915 .name = "sys_clkout2_src",
916 .parent = &func_54m_ck,
917 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
918 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
919 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
920 .init = &omap2_init_clksel_parent,
921 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
922 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
923 .clksel = common_clkout_src_clksel,
794 .recalc = &omap2_clksel_recalc, 924 .recalc = &omap2_clksel_recalc,
925 .round_rate = &omap2_clksel_round_rate,
926 .set_rate = &omap2_clksel_set_rate
927};
928
929static const struct clksel sys_clkout2_clksel[] = {
930 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
931 { .parent = NULL }
795}; 932};
796 933
797/* In 2430, new in 2420 ES2 */ 934/* In 2430, new in 2420 ES2 */
798static struct clk sys_clkout2 = { 935static struct clk sys_clkout2 = {
799 .name = "sys_clkout2", 936 .name = "sys_clkout2",
800 .parent = &func_54m_ck, 937 .parent = &sys_clkout2_src,
801 .rate = 54000000, 938 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
802 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 939 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
803 CM_SYSCLKOUT_SEL1 | RATE_CKCTL, 940 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
804 .src_offset = 8, 941 .clksel = sys_clkout2_clksel,
805 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
806 .enable_bit = 15,
807 .rate_offset = 11,
808 .recalc = &omap2_clksel_recalc, 942 .recalc = &omap2_clksel_recalc,
943 .round_rate = &omap2_clksel_round_rate,
944 .set_rate = &omap2_clksel_set_rate
809}; 945};
810 946
811static struct clk emul_ck = { 947static struct clk emul_ck = {
812 .name = "emul_ck", 948 .name = "emul_ck",
813 .parent = &func_54m_ck, 949 .parent = &func_54m_ck,
814 .flags = CLOCK_IN_OMAP242X, 950 .flags = CLOCK_IN_OMAP242X,
815 .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL, 951 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
816 .enable_bit = 0, 952 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
817 .recalc = &omap2_propagate_rate, 953 .recalc = &followparent_recalc,
818 954
819}; 955};
820#endif /* OLD_CK */ 956
821/* 957/*
822 * MPU clock domain 958 * MPU clock domain
823 * Clocks: 959 * Clocks:
@@ -828,6 +964,20 @@ static struct clk emul_ck = {
828 * - Base divider comes from: CM_CLKSEL_MPU 964 * - Base divider comes from: CM_CLKSEL_MPU
829 * 965 *
830 */ 966 */
967static const struct clksel_rate mpu_core_rates[] = {
968 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
969 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
970 { .div = 4, .val = 4, .flags = RATE_IN_242X },
971 { .div = 6, .val = 6, .flags = RATE_IN_242X },
972 { .div = 8, .val = 8, .flags = RATE_IN_242X },
973 { .div = 0 },
974};
975
976static const struct clksel mpu_clksel[] = {
977 { .parent = &core_ck, .rates = mpu_core_rates },
978 { .parent = NULL }
979};
980
831static struct clk mpu_ck = { /* Control cpu */ 981static struct clk mpu_ck = { /* Control cpu */
832 .name = "mpu_ck", 982 .name = "mpu_ck",
833 .parent = &core_ck, 983 .parent = &core_ck,
@@ -837,85 +987,126 @@ static struct clk mpu_ck = { /* Control cpu */
837 .init = &omap2_init_clksel_parent, 987 .init = &omap2_init_clksel_parent,
838 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 988 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
839 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, 989 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
990 .clksel = mpu_clksel,
840 .recalc = &omap2_clksel_recalc, 991 .recalc = &omap2_clksel_recalc,
841 .round_rate = &omap2_clksel_round_rate, 992 .round_rate = &omap2_clksel_round_rate,
842 .set_rate = &omap2_clksel_set_rate 993 .set_rate = &omap2_clksel_set_rate
843}; 994};
844#ifdef OLD_CK 995
845/* 996/*
846 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain 997 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
847 * Clocks: 998 * Clocks:
848 * 2430: IVA2.1_FCLK, IVA2.1_ICLK 999 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
849 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP 1000 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1001 *
1002 * Won't be too specific here. The core clock comes into this block
1003 * it is divided then tee'ed. One branch goes directly to xyz enable
1004 * controls. The other branch gets further divided by 2 then possibly
1005 * routed into a synchronizer and out of clocks abc.
850 */ 1006 */
851static struct clk iva2_1_fck = { 1007static const struct clksel_rate dsp_fck_core_rates[] = {
852 .name = "iva2_1_fck", 1008 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1009 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1010 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1011 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1012 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1013 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1014 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1015 { .div = 0 },
1016};
1017
1018static const struct clksel dsp_fck_clksel[] = {
1019 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1020 { .parent = NULL }
1021};
1022
1023static struct clk dsp_fck = {
1024 .name = "dsp_fck",
853 .parent = &core_ck, 1025 .parent = &core_ck,
854 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 | 1026 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
855 DELAYED_APP | RATE_PROPAGATES | 1027 CONFIG_PARTICIPANT | RATE_PROPAGATES,
856 CONFIG_PARTICIPANT, 1028 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
857 .rate_offset = 0, 1029 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
858 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, 1030 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
859 .enable_bit = 0, 1031 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1032 .clksel = dsp_fck_clksel,
860 .recalc = &omap2_clksel_recalc, 1033 .recalc = &omap2_clksel_recalc,
1034 .round_rate = &omap2_clksel_round_rate,
1035 .set_rate = &omap2_clksel_set_rate
861}; 1036};
862 1037
863static struct clk iva2_1_ick = { 1038/* DSP interface clock */
864 .name = "iva2_1_ick", 1039static const struct clksel_rate dsp_irate_ick_rates[] = {
865 .parent = &iva2_1_fck, 1040 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
866 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 | 1041 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
867 DELAYED_APP | CONFIG_PARTICIPANT, 1042 { .div = 3, .val = 3, .flags = RATE_IN_243X },
868 .rate_offset = 5, 1043 { .div = 0 },
869 .recalc = &omap2_clksel_recalc, 1044};
1045
1046static const struct clksel dsp_irate_ick_clksel[] = {
1047 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1048 { .parent = NULL }
870}; 1049};
871 1050
872/* 1051/*
873 * Won't be too specific here. The core clock comes into this block 1052 * This clock does not exist as such in the TRM, but is added to
874 * it is divided then tee'ed. One branch goes directly to xyz enable 1053 * separate source selection from XXX
875 * controls. The other branch gets further divided by 2 then possibly
876 * routed into a synchronizer and out of clocks abc.
877 */ 1054 */
878static struct clk dsp_fck = { 1055static struct clk dsp_irate_ick = {
879 .name = "dsp_fck", 1056 .name = "dsp_irate_ick",
880 .parent = &core_ck, 1057 .parent = &dsp_fck,
881 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 | 1058 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
882 DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, 1059 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
883 .rate_offset = 0, 1060 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
884 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, 1061 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
885 .enable_bit = 0, 1062 .clksel = dsp_irate_ick_clksel,
886 .recalc = &omap2_clksel_recalc, 1063 .recalc = &omap2_clksel_recalc,
1064 .round_rate = &omap2_clksel_round_rate,
1065 .set_rate = &omap2_clksel_set_rate
887}; 1066};
888 1067
1068/* 2420 only */
889static struct clk dsp_ick = { 1069static struct clk dsp_ick = {
890 .name = "dsp_ick", /* apparently ipi and isp */ 1070 .name = "dsp_ick", /* apparently ipi and isp */
891 .parent = &dsp_fck, 1071 .parent = &dsp_irate_ick,
892 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 | 1072 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
893 DELAYED_APP | CONFIG_PARTICIPANT, 1073 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
894 .rate_offset = 5, 1074 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
895 .enable_reg = (void __iomem *)&CM_ICLKEN_DSP, 1075};
896 .enable_bit = 1, /* for ipi */ 1076
897 .recalc = &omap2_clksel_recalc, 1077/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1078static struct clk iva2_1_ick = {
1079 .name = "iva2_1_ick",
1080 .parent = &dsp_irate_ick,
1081 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1082 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1083 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
898}; 1084};
899 1085
900static struct clk iva1_ifck = { 1086static struct clk iva1_ifck = {
901 .name = "iva1_ifck", 1087 .name = "iva1_ifck",
902 .parent = &core_ck, 1088 .parent = &core_ck,
903 .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL | 1089 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
904 CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, 1090 RATE_PROPAGATES | DELAYED_APP,
905 .rate_offset= 8, 1091 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
906 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, 1092 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
907 .enable_bit = 10, 1093 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1094 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1095 .clksel = dsp_fck_clksel,
908 .recalc = &omap2_clksel_recalc, 1096 .recalc = &omap2_clksel_recalc,
1097 .round_rate = &omap2_clksel_round_rate,
1098 .set_rate = &omap2_clksel_set_rate
909}; 1099};
910 1100
911/* IVA1 mpu/int/i/f clocks are /2 of parent */ 1101/* IVA1 mpu/int/i/f clocks are /2 of parent */
912static struct clk iva1_mpu_int_ifck = { 1102static struct clk iva1_mpu_int_ifck = {
913 .name = "iva1_mpu_int_ifck", 1103 .name = "iva1_mpu_int_ifck",
914 .parent = &iva1_ifck, 1104 .parent = &iva1_ifck,
915 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1, 1105 .flags = CLOCK_IN_OMAP242X,
916 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, 1106 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
917 .enable_bit = 8, 1107 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
918 .recalc = &omap2_clksel_recalc, 1108 .fixed_div = 2,
1109 .recalc = &omap2_fixed_divisor_recalc,
919}; 1110};
920 1111
921/* 1112/*
@@ -937,27 +1128,62 @@ static struct clk iva1_mpu_int_ifck = {
937 * may very well need notification when the clock changes. Currently for low 1128 * may very well need notification when the clock changes. Currently for low
938 * operating points, these are taken care of in sleep.S. 1129 * operating points, these are taken care of in sleep.S.
939 */ 1130 */
1131static const struct clksel_rate core_l3_core_rates[] = {
1132 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1133 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1134 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1135 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1136 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1137 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1138 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1139 { .div = 0 }
1140};
1141
1142static const struct clksel core_l3_clksel[] = {
1143 { .parent = &core_ck, .rates = core_l3_core_rates },
1144 { .parent = NULL }
1145};
1146
940static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ 1147static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
941 .name = "core_l3_ck", 1148 .name = "core_l3_ck",
942 .parent = &core_ck, 1149 .parent = &core_ck,
943 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1150 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
944 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 | 1151 ALWAYS_ENABLED | DELAYED_APP |
945 DELAYED_APP | CONFIG_PARTICIPANT | 1152 CONFIG_PARTICIPANT | RATE_PROPAGATES,
946 RATE_PROPAGATES, 1153 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
947 .rate_offset = 0, 1154 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1155 .clksel = core_l3_clksel,
948 .recalc = &omap2_clksel_recalc, 1156 .recalc = &omap2_clksel_recalc,
1157 .round_rate = &omap2_clksel_round_rate,
1158 .set_rate = &omap2_clksel_set_rate
1159};
1160
1161/* usb_l4_ick */
1162static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1163 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1164 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1165 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1166 { .div = 0 }
1167};
1168
1169static const struct clksel usb_l4_ick_clksel[] = {
1170 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1171 { .parent = NULL },
949}; 1172};
950 1173
951static struct clk usb_l4_ick = { /* FS-USB interface clock */ 1174static struct clk usb_l4_ick = { /* FS-USB interface clock */
952 .name = "usb_l4_ick", 1175 .name = "usb_l4_ick",
953 .parent = &core_l3_ck, 1176 .parent = &core_l3_ck,
954 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1177 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
955 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP | 1178 DELAYED_APP | CONFIG_PARTICIPANT,
956 CONFIG_PARTICIPANT, 1179 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
957 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 1180 .enable_bit = OMAP24XX_EN_USB_SHIFT,
958 .enable_bit = 0, 1181 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
959 .rate_offset = 25, 1182 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1183 .clksel = usb_l4_ick_clksel,
960 .recalc = &omap2_clksel_recalc, 1184 .recalc = &omap2_clksel_recalc,
1185 .round_rate = &omap2_clksel_round_rate,
1186 .set_rate = &omap2_clksel_set_rate
961}; 1187};
962 1188
963/* 1189/*
@@ -968,15 +1194,35 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
968 * 1194 *
969 * ssr = core/1/2/3/4/5, sst = 1/2 ssr. 1195 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
970 */ 1196 */
1197static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1198 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1199 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1200 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1201 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1202 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1203 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1204 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1205 { .div = 0 }
1206};
1207
1208static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1209 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1210 { .parent = NULL }
1211};
1212
971static struct clk ssi_ssr_sst_fck = { 1213static struct clk ssi_ssr_sst_fck = {
972 .name = "ssi_fck", 1214 .name = "ssi_fck",
973 .parent = &core_ck, 1215 .parent = &core_ck,
974 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1216 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
975 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, 1217 DELAYED_APP,
976 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */ 1218 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
977 .enable_bit = 1, 1219 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
978 .rate_offset = 20, 1220 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1221 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1222 .clksel = ssi_ssr_sst_fck_clksel,
979 .recalc = &omap2_clksel_recalc, 1223 .recalc = &omap2_clksel_recalc,
1224 .round_rate = &omap2_clksel_round_rate,
1225 .set_rate = &omap2_clksel_set_rate
980}; 1226};
981 1227
982/* 1228/*
@@ -990,36 +1236,49 @@ static struct clk ssi_ssr_sst_fck = {
990 * divided value of fclk. 1236 * divided value of fclk.
991 * 1237 *
992 */ 1238 */
1239/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1240
1241/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1242static const struct clksel gfx_fck_clksel[] = {
1243 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1244 { .parent = NULL },
1245};
1246
993static struct clk gfx_3d_fck = { 1247static struct clk gfx_3d_fck = {
994 .name = "gfx_3d_fck", 1248 .name = "gfx_3d_fck",
995 .parent = &core_l3_ck, 1249 .parent = &core_l3_ck,
996 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1250 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
997 RATE_CKCTL | CM_GFX_SEL1, 1251 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
998 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX, 1252 .enable_bit = OMAP24XX_EN_3D_SHIFT,
999 .enable_bit = 2, 1253 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1000 .rate_offset= 0, 1254 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1255 .clksel = gfx_fck_clksel,
1001 .recalc = &omap2_clksel_recalc, 1256 .recalc = &omap2_clksel_recalc,
1257 .round_rate = &omap2_clksel_round_rate,
1258 .set_rate = &omap2_clksel_set_rate
1002}; 1259};
1003 1260
1004static struct clk gfx_2d_fck = { 1261static struct clk gfx_2d_fck = {
1005 .name = "gfx_2d_fck", 1262 .name = "gfx_2d_fck",
1006 .parent = &core_l3_ck, 1263 .parent = &core_l3_ck,
1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1264 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1008 RATE_CKCTL | CM_GFX_SEL1, 1265 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1009 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX, 1266 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1010 .enable_bit = 1, 1267 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1011 .rate_offset= 0, 1268 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1269 .clksel = gfx_fck_clksel,
1012 .recalc = &omap2_clksel_recalc, 1270 .recalc = &omap2_clksel_recalc,
1271 .round_rate = &omap2_clksel_round_rate,
1272 .set_rate = &omap2_clksel_set_rate
1013}; 1273};
1014 1274
1015static struct clk gfx_ick = { 1275static struct clk gfx_ick = {
1016 .name = "gfx_ick", /* From l3 */ 1276 .name = "gfx_ick", /* From l3 */
1017 .parent = &core_l3_ck, 1277 .parent = &core_l3_ck,
1018 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1278 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1019 RATE_CKCTL, 1279 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1020 .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */ 1280 .enable_bit = OMAP_EN_GFX_SHIFT,
1021 .enable_bit = 0, 1281 .recalc = &followparent_recalc,
1022 .recalc = &omap2_followparent_recalc,
1023}; 1282};
1024 1283
1025/* 1284/*
@@ -1027,26 +1286,42 @@ static struct clk gfx_ick = {
1027 * CLOCKS: 1286 * CLOCKS:
1028 * MDM_OSC_CLK 1287 * MDM_OSC_CLK
1029 * MDM_ICLK 1288 * MDM_ICLK
1289 * These clocks are usable in chassis mode only.
1030 */ 1290 */
1291static const struct clksel_rate mdm_ick_core_rates[] = {
1292 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1293 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1294 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1295 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1296 { .div = 0 }
1297};
1298
1299static const struct clksel mdm_ick_clksel[] = {
1300 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1301 { .parent = NULL }
1302};
1303
1031static struct clk mdm_ick = { /* used both as a ick and fck */ 1304static struct clk mdm_ick = { /* used both as a ick and fck */
1032 .name = "mdm_ick", 1305 .name = "mdm_ick",
1033 .parent = &core_ck, 1306 .parent = &core_ck,
1034 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 | 1307 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1035 DELAYED_APP | CONFIG_PARTICIPANT, 1308 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1036 .rate_offset = 0, 1309 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1037 .enable_reg = (void __iomem *)&CM_ICLKEN_MDM, 1310 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1038 .enable_bit = 0, 1311 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1312 .clksel = mdm_ick_clksel,
1039 .recalc = &omap2_clksel_recalc, 1313 .recalc = &omap2_clksel_recalc,
1314 .round_rate = &omap2_clksel_round_rate,
1315 .set_rate = &omap2_clksel_set_rate
1040}; 1316};
1041 1317
1042static struct clk mdm_osc_ck = { 1318static struct clk mdm_osc_ck = {
1043 .name = "mdm_osc_ck", 1319 .name = "mdm_osc_ck",
1044 .rate = 26000000,
1045 .parent = &osc_ck, 1320 .parent = &osc_ck,
1046 .flags = CLOCK_IN_OMAP243X | RATE_FIXED, 1321 .flags = CLOCK_IN_OMAP243X,
1047 .enable_reg = (void __iomem *)&CM_FCLKEN_MDM, 1322 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1048 .enable_bit = 1, 1323 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1049 .recalc = &omap2_followparent_recalc, 1324 .recalc = &followparent_recalc,
1050}; 1325};
1051 1326
1052/* 1327/*
@@ -1056,23 +1331,37 @@ static struct clk mdm_osc_ck = {
1056 * functional clocks. Fixed APLL functional source clocks are managed in 1331 * functional clocks. Fixed APLL functional source clocks are managed in
1057 * this domain. 1332 * this domain.
1058 */ 1333 */
1334static const struct clksel_rate l4_core_l3_rates[] = {
1335 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1336 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1337 { .div = 0 }
1338};
1339
1340static const struct clksel l4_clksel[] = {
1341 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1342 { .parent = NULL }
1343};
1344
1059static struct clk l4_ck = { /* used both as an ick and fck */ 1345static struct clk l4_ck = { /* used both as an ick and fck */
1060 .name = "l4_ck", 1346 .name = "l4_ck",
1061 .parent = &core_l3_ck, 1347 .parent = &core_l3_ck,
1062 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1348 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1063 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 | 1349 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1064 DELAYED_APP | RATE_PROPAGATES, 1350 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1065 .rate_offset = 5, 1351 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1352 .clksel = l4_clksel,
1066 .recalc = &omap2_clksel_recalc, 1353 .recalc = &omap2_clksel_recalc,
1354 .round_rate = &omap2_clksel_round_rate,
1355 .set_rate = &omap2_clksel_set_rate
1067}; 1356};
1068 1357
1069static struct clk ssi_l4_ick = { 1358static struct clk ssi_l4_ick = {
1070 .name = "ssi_l4_ick", 1359 .name = "ssi_l4_ick",
1071 .parent = &l4_ck, 1360 .parent = &l4_ck,
1072 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL, 1361 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1073 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */ 1362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1074 .enable_bit = 1, 1363 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1075 .recalc = &omap2_followparent_recalc, 1364 .recalc = &followparent_recalc,
1076}; 1365};
1077 1366
1078/* 1367/*
@@ -1083,48 +1372,95 @@ static struct clk ssi_l4_ick = {
1083 * 1372 *
1084 * DSS is both initiator and target. 1373 * DSS is both initiator and target.
1085 */ 1374 */
1375/* XXX Add RATE_NOT_VALIDATED */
1376
1377static const struct clksel_rate dss1_fck_sys_rates[] = {
1378 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1379 { .div = 0 }
1380};
1381
1382static const struct clksel_rate dss1_fck_core_rates[] = {
1383 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1384 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1385 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1386 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1387 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1388 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1389 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1390 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1391 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1392 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1393 { .div = 0 }
1394};
1395
1396static const struct clksel dss1_fck_clksel[] = {
1397 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1398 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1399 { .parent = NULL },
1400};
1401
1086static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 1402static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1087 .name = "dss_ick", 1403 .name = "dss_ick",
1088 .parent = &l4_ck, /* really both l3 and l4 */ 1404 .parent = &l4_ck, /* really both l3 and l4 */
1089 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL, 1405 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1090 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1406 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1091 .enable_bit = 0, 1407 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1092 .recalc = &omap2_followparent_recalc, 1408 .recalc = &followparent_recalc,
1093}; 1409};
1094 1410
1095static struct clk dss1_fck = { 1411static struct clk dss1_fck = {
1096 .name = "dss1_fck", 1412 .name = "dss1_fck",
1097 .parent = &core_ck, /* Core or sys */ 1413 .parent = &core_ck, /* Core or sys */
1098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1414 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1099 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, 1415 DELAYED_APP,
1100 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1101 .enable_bit = 0, 1417 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1102 .rate_offset = 8, 1418 .init = &omap2_init_clksel_parent,
1103 .src_offset = 8, 1419 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1420 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1421 .clksel = dss1_fck_clksel,
1104 .recalc = &omap2_clksel_recalc, 1422 .recalc = &omap2_clksel_recalc,
1423 .round_rate = &omap2_clksel_round_rate,
1424 .set_rate = &omap2_clksel_set_rate
1425};
1426
1427static const struct clksel_rate dss2_fck_sys_rates[] = {
1428 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1429 { .div = 0 }
1430};
1431
1432static const struct clksel_rate dss2_fck_48m_rates[] = {
1433 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1434 { .div = 0 }
1435};
1436
1437static const struct clksel dss2_fck_clksel[] = {
1438 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1439 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1440 { .parent = NULL }
1105}; 1441};
1106 1442
1107static struct clk dss2_fck = { /* Alt clk used in power management */ 1443static struct clk dss2_fck = { /* Alt clk used in power management */
1108 .name = "dss2_fck", 1444 .name = "dss2_fck",
1109 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1445 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1110 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1446 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1111 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1112 DELAYED_APP, 1447 DELAYED_APP,
1113 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1114 .enable_bit = 1, 1449 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1115 .src_offset = 13, 1450 .init = &omap2_init_clksel_parent,
1116 .recalc = &omap2_followparent_recalc, 1451 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1452 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1453 .clksel = dss2_fck_clksel,
1454 .recalc = &followparent_recalc,
1117}; 1455};
1118 1456
1119static struct clk dss_54m_fck = { /* Alt clk used in power management */ 1457static struct clk dss_54m_fck = { /* Alt clk used in power management */
1120 .name = "dss_54m_fck", /* 54m tv clk */ 1458 .name = "dss_54m_fck", /* 54m tv clk */
1121 .parent = &func_54m_ck, 1459 .parent = &func_54m_ck,
1122 .rate = 54000000, 1460 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1123 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1124 RATE_FIXED | RATE_PROPAGATES, 1462 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1125 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1463 .recalc = &followparent_recalc,
1126 .enable_bit = 2,
1127 .recalc = &omap2_propagate_rate,
1128}; 1464};
1129 1465
1130/* 1466/*
@@ -1133,334 +1469,372 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
1133 * here will likely have an L4 interface parent, and may have multiple 1469 * here will likely have an L4 interface parent, and may have multiple
1134 * functional clock parents. 1470 * functional clock parents.
1135 */ 1471 */
1472static const struct clksel_rate gpt_alt_rates[] = {
1473 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1474 { .div = 0 }
1475};
1476
1477static const struct clksel omap24xx_gpt_clksel[] = {
1478 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1479 { .parent = &sys_ck, .rates = gpt_sys_rates },
1480 { .parent = &alt_ck, .rates = gpt_alt_rates },
1481 { .parent = NULL },
1482};
1483
1136static struct clk gpt1_ick = { 1484static struct clk gpt1_ick = {
1137 .name = "gpt1_ick", 1485 .name = "gpt1_ick",
1138 .parent = &l4_ck, 1486 .parent = &l4_ck,
1139 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1487 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1140 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */ 1488 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1141 .enable_bit = 0, 1489 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1142 .recalc = &omap2_followparent_recalc, 1490 .recalc = &followparent_recalc,
1143}; 1491};
1144 1492
1145static struct clk gpt1_fck = { 1493static struct clk gpt1_fck = {
1146 .name = "gpt1_fck", 1494 .name = "gpt1_fck",
1147 .parent = &func_32k_ck, 1495 .parent = &func_32k_ck,
1148 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1496 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1149 CM_WKUP_SEL1, 1497 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1150 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */ 1498 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1151 .enable_bit = 0, 1499 .init = &omap2_init_clksel_parent,
1152 .src_offset = 0, 1500 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1153 .recalc = &omap2_followparent_recalc, 1501 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1502 .clksel = omap24xx_gpt_clksel,
1503 .recalc = &omap2_clksel_recalc,
1504 .round_rate = &omap2_clksel_round_rate,
1505 .set_rate = &omap2_clksel_set_rate
1154}; 1506};
1155 1507
1156static struct clk gpt2_ick = { 1508static struct clk gpt2_ick = {
1157 .name = "gpt2_ick", 1509 .name = "gpt2_ick",
1158 .parent = &l4_ck, 1510 .parent = &l4_ck,
1159 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1511 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1160 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */ 1512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1161 .enable_bit = 4, 1513 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1162 .recalc = &omap2_followparent_recalc, 1514 .recalc = &followparent_recalc,
1163}; 1515};
1164 1516
1165static struct clk gpt2_fck = { 1517static struct clk gpt2_fck = {
1166 .name = "gpt2_fck", 1518 .name = "gpt2_fck",
1167 .parent = &func_32k_ck, 1519 .parent = &func_32k_ck,
1168 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1520 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1169 CM_CORE_SEL2, 1521 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1170 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1522 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1171 .enable_bit = 4, 1523 .init = &omap2_init_clksel_parent,
1172 .src_offset = 2, 1524 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1173 .recalc = &omap2_followparent_recalc, 1525 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1526 .clksel = omap24xx_gpt_clksel,
1527 .recalc = &omap2_clksel_recalc,
1174}; 1528};
1175 1529
1176static struct clk gpt3_ick = { 1530static struct clk gpt3_ick = {
1177 .name = "gpt3_ick", 1531 .name = "gpt3_ick",
1178 .parent = &l4_ck, 1532 .parent = &l4_ck,
1179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1533 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1180 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */ 1534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1181 .enable_bit = 5, 1535 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1182 .recalc = &omap2_followparent_recalc, 1536 .recalc = &followparent_recalc,
1183}; 1537};
1184 1538
1185static struct clk gpt3_fck = { 1539static struct clk gpt3_fck = {
1186 .name = "gpt3_fck", 1540 .name = "gpt3_fck",
1187 .parent = &func_32k_ck, 1541 .parent = &func_32k_ck,
1188 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1542 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1189 CM_CORE_SEL2, 1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1190 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1544 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1191 .enable_bit = 5, 1545 .init = &omap2_init_clksel_parent,
1192 .src_offset = 4, 1546 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1193 .recalc = &omap2_followparent_recalc, 1547 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1548 .clksel = omap24xx_gpt_clksel,
1549 .recalc = &omap2_clksel_recalc,
1194}; 1550};
1195 1551
1196static struct clk gpt4_ick = { 1552static struct clk gpt4_ick = {
1197 .name = "gpt4_ick", 1553 .name = "gpt4_ick",
1198 .parent = &l4_ck, 1554 .parent = &l4_ck,
1199 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1555 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1200 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */ 1556 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1201 .enable_bit = 6, 1557 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1202 .recalc = &omap2_followparent_recalc, 1558 .recalc = &followparent_recalc,
1203}; 1559};
1204 1560
1205static struct clk gpt4_fck = { 1561static struct clk gpt4_fck = {
1206 .name = "gpt4_fck", 1562 .name = "gpt4_fck",
1207 .parent = &func_32k_ck, 1563 .parent = &func_32k_ck,
1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1564 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1209 CM_CORE_SEL2, 1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1210 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1566 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1211 .enable_bit = 6, 1567 .init = &omap2_init_clksel_parent,
1212 .src_offset = 6, 1568 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1213 .recalc = &omap2_followparent_recalc, 1569 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1570 .clksel = omap24xx_gpt_clksel,
1571 .recalc = &omap2_clksel_recalc,
1214}; 1572};
1215 1573
1216static struct clk gpt5_ick = { 1574static struct clk gpt5_ick = {
1217 .name = "gpt5_ick", 1575 .name = "gpt5_ick",
1218 .parent = &l4_ck, 1576 .parent = &l4_ck,
1219 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1577 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1220 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */ 1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1221 .enable_bit = 7, 1579 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1222 .recalc = &omap2_followparent_recalc, 1580 .recalc = &followparent_recalc,
1223}; 1581};
1224 1582
1225static struct clk gpt5_fck = { 1583static struct clk gpt5_fck = {
1226 .name = "gpt5_fck", 1584 .name = "gpt5_fck",
1227 .parent = &func_32k_ck, 1585 .parent = &func_32k_ck,
1228 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1586 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1229 CM_CORE_SEL2, 1587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1230 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1588 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1231 .enable_bit = 7, 1589 .init = &omap2_init_clksel_parent,
1232 .src_offset = 8, 1590 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1233 .recalc = &omap2_followparent_recalc, 1591 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1592 .clksel = omap24xx_gpt_clksel,
1593 .recalc = &omap2_clksel_recalc,
1234}; 1594};
1235 1595
1236static struct clk gpt6_ick = { 1596static struct clk gpt6_ick = {
1237 .name = "gpt6_ick", 1597 .name = "gpt6_ick",
1238 .parent = &l4_ck, 1598 .parent = &l4_ck,
1239 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1599 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1240 .enable_bit = 8, 1600 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1241 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */ 1601 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1242 .recalc = &omap2_followparent_recalc, 1602 .recalc = &followparent_recalc,
1243}; 1603};
1244 1604
1245static struct clk gpt6_fck = { 1605static struct clk gpt6_fck = {
1246 .name = "gpt6_fck", 1606 .name = "gpt6_fck",
1247 .parent = &func_32k_ck, 1607 .parent = &func_32k_ck,
1248 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1608 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1249 CM_CORE_SEL2, 1609 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1250 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1610 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1251 .enable_bit = 8, 1611 .init = &omap2_init_clksel_parent,
1252 .src_offset = 10, 1612 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1253 .recalc = &omap2_followparent_recalc, 1613 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1614 .clksel = omap24xx_gpt_clksel,
1615 .recalc = &omap2_clksel_recalc,
1254}; 1616};
1255 1617
1256static struct clk gpt7_ick = { 1618static struct clk gpt7_ick = {
1257 .name = "gpt7_ick", 1619 .name = "gpt7_ick",
1258 .parent = &l4_ck, 1620 .parent = &l4_ck,
1259 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1621 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1260 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */ 1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1261 .enable_bit = 9, 1623 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1262 .recalc = &omap2_followparent_recalc, 1624 .recalc = &followparent_recalc,
1263}; 1625};
1264 1626
1265static struct clk gpt7_fck = { 1627static struct clk gpt7_fck = {
1266 .name = "gpt7_fck", 1628 .name = "gpt7_fck",
1267 .parent = &func_32k_ck, 1629 .parent = &func_32k_ck,
1268 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1269 CM_CORE_SEL2, 1631 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1270 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1632 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1271 .enable_bit = 9, 1633 .init = &omap2_init_clksel_parent,
1272 .src_offset = 12, 1634 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1273 .recalc = &omap2_followparent_recalc, 1635 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1636 .clksel = omap24xx_gpt_clksel,
1637 .recalc = &omap2_clksel_recalc,
1274}; 1638};
1275 1639
1276static struct clk gpt8_ick = { 1640static struct clk gpt8_ick = {
1277 .name = "gpt8_ick", 1641 .name = "gpt8_ick",
1278 .parent = &l4_ck, 1642 .parent = &l4_ck,
1279 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1643 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1280 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */ 1644 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1281 .enable_bit = 10, 1645 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1282 .recalc = &omap2_followparent_recalc, 1646 .recalc = &followparent_recalc,
1283}; 1647};
1284 1648
1285static struct clk gpt8_fck = { 1649static struct clk gpt8_fck = {
1286 .name = "gpt8_fck", 1650 .name = "gpt8_fck",
1287 .parent = &func_32k_ck, 1651 .parent = &func_32k_ck,
1288 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1652 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1289 CM_CORE_SEL2, 1653 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1290 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1654 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1291 .enable_bit = 10, 1655 .init = &omap2_init_clksel_parent,
1292 .src_offset = 14, 1656 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1293 .recalc = &omap2_followparent_recalc, 1657 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1658 .clksel = omap24xx_gpt_clksel,
1659 .recalc = &omap2_clksel_recalc,
1294}; 1660};
1295 1661
1296static struct clk gpt9_ick = { 1662static struct clk gpt9_ick = {
1297 .name = "gpt9_ick", 1663 .name = "gpt9_ick",
1298 .parent = &l4_ck, 1664 .parent = &l4_ck,
1299 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1665 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1300 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1666 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1301 .enable_bit = 11, 1667 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1302 .recalc = &omap2_followparent_recalc, 1668 .recalc = &followparent_recalc,
1303}; 1669};
1304 1670
1305static struct clk gpt9_fck = { 1671static struct clk gpt9_fck = {
1306 .name = "gpt9_fck", 1672 .name = "gpt9_fck",
1307 .parent = &func_32k_ck, 1673 .parent = &func_32k_ck,
1308 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1674 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1309 CM_CORE_SEL2, 1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1310 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1676 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1311 .enable_bit = 11, 1677 .init = &omap2_init_clksel_parent,
1312 .src_offset = 16, 1678 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1313 .recalc = &omap2_followparent_recalc, 1679 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1680 .clksel = omap24xx_gpt_clksel,
1681 .recalc = &omap2_clksel_recalc,
1314}; 1682};
1315 1683
1316static struct clk gpt10_ick = { 1684static struct clk gpt10_ick = {
1317 .name = "gpt10_ick", 1685 .name = "gpt10_ick",
1318 .parent = &l4_ck, 1686 .parent = &l4_ck,
1319 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1687 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1320 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1321 .enable_bit = 12, 1689 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1322 .recalc = &omap2_followparent_recalc, 1690 .recalc = &followparent_recalc,
1323}; 1691};
1324 1692
1325static struct clk gpt10_fck = { 1693static struct clk gpt10_fck = {
1326 .name = "gpt10_fck", 1694 .name = "gpt10_fck",
1327 .parent = &func_32k_ck, 1695 .parent = &func_32k_ck,
1328 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1696 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1329 CM_CORE_SEL2, 1697 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1330 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1698 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1331 .enable_bit = 12, 1699 .init = &omap2_init_clksel_parent,
1332 .src_offset = 18, 1700 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1333 .recalc = &omap2_followparent_recalc, 1701 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1702 .clksel = omap24xx_gpt_clksel,
1703 .recalc = &omap2_clksel_recalc,
1334}; 1704};
1335 1705
1336static struct clk gpt11_ick = { 1706static struct clk gpt11_ick = {
1337 .name = "gpt11_ick", 1707 .name = "gpt11_ick",
1338 .parent = &l4_ck, 1708 .parent = &l4_ck,
1339 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1709 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1340 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1710 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1341 .enable_bit = 13, 1711 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1342 .recalc = &omap2_followparent_recalc, 1712 .recalc = &followparent_recalc,
1343}; 1713};
1344 1714
1345static struct clk gpt11_fck = { 1715static struct clk gpt11_fck = {
1346 .name = "gpt11_fck", 1716 .name = "gpt11_fck",
1347 .parent = &func_32k_ck, 1717 .parent = &func_32k_ck,
1348 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1718 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1349 CM_CORE_SEL2, 1719 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1350 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1720 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1351 .enable_bit = 13, 1721 .init = &omap2_init_clksel_parent,
1352 .src_offset = 20, 1722 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1353 .recalc = &omap2_followparent_recalc, 1723 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1724 .clksel = omap24xx_gpt_clksel,
1725 .recalc = &omap2_clksel_recalc,
1354}; 1726};
1355 1727
1356static struct clk gpt12_ick = { 1728static struct clk gpt12_ick = {
1357 .name = "gpt12_ick", 1729 .name = "gpt12_ick",
1358 .parent = &l4_ck, 1730 .parent = &l4_ck,
1359 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1731 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1360 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */ 1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1361 .enable_bit = 14, 1733 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1362 .recalc = &omap2_followparent_recalc, 1734 .recalc = &followparent_recalc,
1363}; 1735};
1364 1736
1365static struct clk gpt12_fck = { 1737static struct clk gpt12_fck = {
1366 .name = "gpt12_fck", 1738 .name = "gpt12_fck",
1367 .parent = &func_32k_ck, 1739 .parent = &func_32k_ck,
1368 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1740 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1369 CM_CORE_SEL2, 1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1370 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1742 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1371 .enable_bit = 14, 1743 .init = &omap2_init_clksel_parent,
1372 .src_offset = 22, 1744 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1373 .recalc = &omap2_followparent_recalc, 1745 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1746 .clksel = omap24xx_gpt_clksel,
1747 .recalc = &omap2_clksel_recalc,
1374}; 1748};
1375 1749
1376static struct clk mcbsp1_ick = { 1750static struct clk mcbsp1_ick = {
1377 .name = "mcbsp1_ick", 1751 .name = "mcbsp1_ick",
1378 .parent = &l4_ck, 1752 .parent = &l4_ck,
1379 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1753 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1380 .enable_bit = 15, 1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1381 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */ 1755 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1382 .recalc = &omap2_followparent_recalc, 1756 .recalc = &followparent_recalc,
1383}; 1757};
1384 1758
1385static struct clk mcbsp1_fck = { 1759static struct clk mcbsp1_fck = {
1386 .name = "mcbsp1_fck", 1760 .name = "mcbsp1_fck",
1387 .parent = &func_96m_ck, 1761 .parent = &func_96m_ck,
1388 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1762 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1389 .enable_bit = 15, 1763 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1390 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1764 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1391 .recalc = &omap2_followparent_recalc, 1765 .recalc = &followparent_recalc,
1392}; 1766};
1393 1767
1394static struct clk mcbsp2_ick = { 1768static struct clk mcbsp2_ick = {
1395 .name = "mcbsp2_ick", 1769 .name = "mcbsp2_ick",
1396 .parent = &l4_ck, 1770 .parent = &l4_ck,
1397 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1771 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1398 .enable_bit = 16, 1772 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1399 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1773 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1400 .recalc = &omap2_followparent_recalc, 1774 .recalc = &followparent_recalc,
1401}; 1775};
1402 1776
1403static struct clk mcbsp2_fck = { 1777static struct clk mcbsp2_fck = {
1404 .name = "mcbsp2_fck", 1778 .name = "mcbsp2_fck",
1405 .parent = &func_96m_ck, 1779 .parent = &func_96m_ck,
1406 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1407 .enable_bit = 16, 1781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1408 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1782 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1409 .recalc = &omap2_followparent_recalc, 1783 .recalc = &followparent_recalc,
1410}; 1784};
1411 1785
1412static struct clk mcbsp3_ick = { 1786static struct clk mcbsp3_ick = {
1413 .name = "mcbsp3_ick", 1787 .name = "mcbsp3_ick",
1414 .parent = &l4_ck, 1788 .parent = &l4_ck,
1415 .flags = CLOCK_IN_OMAP243X, 1789 .flags = CLOCK_IN_OMAP243X,
1416 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1417 .enable_bit = 3, 1791 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1418 .recalc = &omap2_followparent_recalc, 1792 .recalc = &followparent_recalc,
1419}; 1793};
1420 1794
1421static struct clk mcbsp3_fck = { 1795static struct clk mcbsp3_fck = {
1422 .name = "mcbsp3_fck", 1796 .name = "mcbsp3_fck",
1423 .parent = &func_96m_ck, 1797 .parent = &func_96m_ck,
1424 .flags = CLOCK_IN_OMAP243X, 1798 .flags = CLOCK_IN_OMAP243X,
1425 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1426 .enable_bit = 3, 1800 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1427 .recalc = &omap2_followparent_recalc, 1801 .recalc = &followparent_recalc,
1428}; 1802};
1429 1803
1430static struct clk mcbsp4_ick = { 1804static struct clk mcbsp4_ick = {
1431 .name = "mcbsp4_ick", 1805 .name = "mcbsp4_ick",
1432 .parent = &l4_ck, 1806 .parent = &l4_ck,
1433 .flags = CLOCK_IN_OMAP243X, 1807 .flags = CLOCK_IN_OMAP243X,
1434 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 1808 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1435 .enable_bit = 4, 1809 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1436 .recalc = &omap2_followparent_recalc, 1810 .recalc = &followparent_recalc,
1437}; 1811};
1438 1812
1439static struct clk mcbsp4_fck = { 1813static struct clk mcbsp4_fck = {
1440 .name = "mcbsp4_fck", 1814 .name = "mcbsp4_fck",
1441 .parent = &func_96m_ck, 1815 .parent = &func_96m_ck,
1442 .flags = CLOCK_IN_OMAP243X, 1816 .flags = CLOCK_IN_OMAP243X,
1443 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 1817 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1444 .enable_bit = 4, 1818 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1445 .recalc = &omap2_followparent_recalc, 1819 .recalc = &followparent_recalc,
1446}; 1820};
1447 1821
1448static struct clk mcbsp5_ick = { 1822static struct clk mcbsp5_ick = {
1449 .name = "mcbsp5_ick", 1823 .name = "mcbsp5_ick",
1450 .parent = &l4_ck, 1824 .parent = &l4_ck,
1451 .flags = CLOCK_IN_OMAP243X, 1825 .flags = CLOCK_IN_OMAP243X,
1452 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 1826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1453 .enable_bit = 5, 1827 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1454 .recalc = &omap2_followparent_recalc, 1828 .recalc = &followparent_recalc,
1455}; 1829};
1456 1830
1457static struct clk mcbsp5_fck = { 1831static struct clk mcbsp5_fck = {
1458 .name = "mcbsp5_fck", 1832 .name = "mcbsp5_fck",
1459 .parent = &func_96m_ck, 1833 .parent = &func_96m_ck,
1460 .flags = CLOCK_IN_OMAP243X, 1834 .flags = CLOCK_IN_OMAP243X,
1461 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 1835 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1462 .enable_bit = 5, 1836 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1463 .recalc = &omap2_followparent_recalc, 1837 .recalc = &followparent_recalc,
1464}; 1838};
1465 1839
1466static struct clk mcspi1_ick = { 1840static struct clk mcspi1_ick = {
@@ -1468,9 +1842,9 @@ static struct clk mcspi1_ick = {
1468 .id = 1, 1842 .id = 1,
1469 .parent = &l4_ck, 1843 .parent = &l4_ck,
1470 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1844 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1471 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1845 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1472 .enable_bit = 17, 1846 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1473 .recalc = &omap2_followparent_recalc, 1847 .recalc = &followparent_recalc,
1474}; 1848};
1475 1849
1476static struct clk mcspi1_fck = { 1850static struct clk mcspi1_fck = {
@@ -1478,9 +1852,9 @@ static struct clk mcspi1_fck = {
1478 .id = 1, 1852 .id = 1,
1479 .parent = &func_48m_ck, 1853 .parent = &func_48m_ck,
1480 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1854 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1481 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1855 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1482 .enable_bit = 17, 1856 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1483 .recalc = &omap2_followparent_recalc, 1857 .recalc = &followparent_recalc,
1484}; 1858};
1485 1859
1486static struct clk mcspi2_ick = { 1860static struct clk mcspi2_ick = {
@@ -1488,9 +1862,9 @@ static struct clk mcspi2_ick = {
1488 .id = 2, 1862 .id = 2,
1489 .parent = &l4_ck, 1863 .parent = &l4_ck,
1490 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1864 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1491 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1492 .enable_bit = 18, 1866 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1493 .recalc = &omap2_followparent_recalc, 1867 .recalc = &followparent_recalc,
1494}; 1868};
1495 1869
1496static struct clk mcspi2_fck = { 1870static struct clk mcspi2_fck = {
@@ -1498,9 +1872,9 @@ static struct clk mcspi2_fck = {
1498 .id = 2, 1872 .id = 2,
1499 .parent = &func_48m_ck, 1873 .parent = &func_48m_ck,
1500 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1874 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1501 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1875 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1502 .enable_bit = 18, 1876 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1503 .recalc = &omap2_followparent_recalc, 1877 .recalc = &followparent_recalc,
1504}; 1878};
1505 1879
1506static struct clk mcspi3_ick = { 1880static struct clk mcspi3_ick = {
@@ -1508,9 +1882,9 @@ static struct clk mcspi3_ick = {
1508 .id = 3, 1882 .id = 3,
1509 .parent = &l4_ck, 1883 .parent = &l4_ck,
1510 .flags = CLOCK_IN_OMAP243X, 1884 .flags = CLOCK_IN_OMAP243X,
1511 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1512 .enable_bit = 9, 1886 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1513 .recalc = &omap2_followparent_recalc, 1887 .recalc = &followparent_recalc,
1514}; 1888};
1515 1889
1516static struct clk mcspi3_fck = { 1890static struct clk mcspi3_fck = {
@@ -1518,285 +1892,285 @@ static struct clk mcspi3_fck = {
1518 .id = 3, 1892 .id = 3,
1519 .parent = &func_48m_ck, 1893 .parent = &func_48m_ck,
1520 .flags = CLOCK_IN_OMAP243X, 1894 .flags = CLOCK_IN_OMAP243X,
1521 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1522 .enable_bit = 9, 1896 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1523 .recalc = &omap2_followparent_recalc, 1897 .recalc = &followparent_recalc,
1524}; 1898};
1525 1899
1526static struct clk uart1_ick = { 1900static struct clk uart1_ick = {
1527 .name = "uart1_ick", 1901 .name = "uart1_ick",
1528 .parent = &l4_ck, 1902 .parent = &l4_ck,
1529 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1903 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1530 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1904 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1531 .enable_bit = 21, 1905 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1532 .recalc = &omap2_followparent_recalc, 1906 .recalc = &followparent_recalc,
1533}; 1907};
1534 1908
1535static struct clk uart1_fck = { 1909static struct clk uart1_fck = {
1536 .name = "uart1_fck", 1910 .name = "uart1_fck",
1537 .parent = &func_48m_ck, 1911 .parent = &func_48m_ck,
1538 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1912 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1539 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1540 .enable_bit = 21, 1914 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1541 .recalc = &omap2_followparent_recalc, 1915 .recalc = &followparent_recalc,
1542}; 1916};
1543 1917
1544static struct clk uart2_ick = { 1918static struct clk uart2_ick = {
1545 .name = "uart2_ick", 1919 .name = "uart2_ick",
1546 .parent = &l4_ck, 1920 .parent = &l4_ck,
1547 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1921 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1548 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1549 .enable_bit = 22, 1923 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1550 .recalc = &omap2_followparent_recalc, 1924 .recalc = &followparent_recalc,
1551}; 1925};
1552 1926
1553static struct clk uart2_fck = { 1927static struct clk uart2_fck = {
1554 .name = "uart2_fck", 1928 .name = "uart2_fck",
1555 .parent = &func_48m_ck, 1929 .parent = &func_48m_ck,
1556 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1930 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1557 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1558 .enable_bit = 22, 1932 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1559 .recalc = &omap2_followparent_recalc, 1933 .recalc = &followparent_recalc,
1560}; 1934};
1561 1935
1562static struct clk uart3_ick = { 1936static struct clk uart3_ick = {
1563 .name = "uart3_ick", 1937 .name = "uart3_ick",
1564 .parent = &l4_ck, 1938 .parent = &l4_ck,
1565 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1939 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1566 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1567 .enable_bit = 2, 1941 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1568 .recalc = &omap2_followparent_recalc, 1942 .recalc = &followparent_recalc,
1569}; 1943};
1570 1944
1571static struct clk uart3_fck = { 1945static struct clk uart3_fck = {
1572 .name = "uart3_fck", 1946 .name = "uart3_fck",
1573 .parent = &func_48m_ck, 1947 .parent = &func_48m_ck,
1574 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1948 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1575 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 1949 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1576 .enable_bit = 2, 1950 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1577 .recalc = &omap2_followparent_recalc, 1951 .recalc = &followparent_recalc,
1578}; 1952};
1579 1953
1580static struct clk gpios_ick = { 1954static struct clk gpios_ick = {
1581 .name = "gpios_ick", 1955 .name = "gpios_ick",
1582 .parent = &l4_ck, 1956 .parent = &l4_ck,
1583 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1957 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1584 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, 1958 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1585 .enable_bit = 2, 1959 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1586 .recalc = &omap2_followparent_recalc, 1960 .recalc = &followparent_recalc,
1587}; 1961};
1588 1962
1589static struct clk gpios_fck = { 1963static struct clk gpios_fck = {
1590 .name = "gpios_fck", 1964 .name = "gpios_fck",
1591 .parent = &func_32k_ck, 1965 .parent = &func_32k_ck,
1592 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1966 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1593 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, 1967 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1594 .enable_bit = 2, 1968 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1595 .recalc = &omap2_followparent_recalc, 1969 .recalc = &followparent_recalc,
1596}; 1970};
1597 1971
1598static struct clk mpu_wdt_ick = { 1972static struct clk mpu_wdt_ick = {
1599 .name = "mpu_wdt_ick", 1973 .name = "mpu_wdt_ick",
1600 .parent = &l4_ck, 1974 .parent = &l4_ck,
1601 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1975 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1602 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, 1976 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1603 .enable_bit = 3, 1977 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1604 .recalc = &omap2_followparent_recalc, 1978 .recalc = &followparent_recalc,
1605}; 1979};
1606 1980
1607static struct clk mpu_wdt_fck = { 1981static struct clk mpu_wdt_fck = {
1608 .name = "mpu_wdt_fck", 1982 .name = "mpu_wdt_fck",
1609 .parent = &func_32k_ck, 1983 .parent = &func_32k_ck,
1610 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1984 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1611 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, 1985 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1612 .enable_bit = 3, 1986 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1613 .recalc = &omap2_followparent_recalc, 1987 .recalc = &followparent_recalc,
1614}; 1988};
1615 1989
1616static struct clk sync_32k_ick = { 1990static struct clk sync_32k_ick = {
1617 .name = "sync_32k_ick", 1991 .name = "sync_32k_ick",
1618 .parent = &l4_ck, 1992 .parent = &l4_ck,
1619 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1993 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1620 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, 1994 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1621 .enable_bit = 1, 1995 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1622 .recalc = &omap2_followparent_recalc, 1996 .recalc = &followparent_recalc,
1623}; 1997};
1624static struct clk wdt1_ick = { 1998static struct clk wdt1_ick = {
1625 .name = "wdt1_ick", 1999 .name = "wdt1_ick",
1626 .parent = &l4_ck, 2000 .parent = &l4_ck,
1627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2001 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1628 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, 2002 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1629 .enable_bit = 4, 2003 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1630 .recalc = &omap2_followparent_recalc, 2004 .recalc = &followparent_recalc,
1631}; 2005};
1632static struct clk omapctrl_ick = { 2006static struct clk omapctrl_ick = {
1633 .name = "omapctrl_ick", 2007 .name = "omapctrl_ick",
1634 .parent = &l4_ck, 2008 .parent = &l4_ck,
1635 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2009 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1636 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, 2010 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1637 .enable_bit = 5, 2011 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1638 .recalc = &omap2_followparent_recalc, 2012 .recalc = &followparent_recalc,
1639}; 2013};
1640static struct clk icr_ick = { 2014static struct clk icr_ick = {
1641 .name = "icr_ick", 2015 .name = "icr_ick",
1642 .parent = &l4_ck, 2016 .parent = &l4_ck,
1643 .flags = CLOCK_IN_OMAP243X, 2017 .flags = CLOCK_IN_OMAP243X,
1644 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, 2018 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1645 .enable_bit = 6, 2019 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1646 .recalc = &omap2_followparent_recalc, 2020 .recalc = &followparent_recalc,
1647}; 2021};
1648 2022
1649static struct clk cam_ick = { 2023static struct clk cam_ick = {
1650 .name = "cam_ick", 2024 .name = "cam_ick",
1651 .parent = &l4_ck, 2025 .parent = &l4_ck,
1652 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2026 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2027 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1654 .enable_bit = 31, 2028 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1655 .recalc = &omap2_followparent_recalc, 2029 .recalc = &followparent_recalc,
1656}; 2030};
1657 2031
1658static struct clk cam_fck = { 2032static struct clk cam_fck = {
1659 .name = "cam_fck", 2033 .name = "cam_fck",
1660 .parent = &func_96m_ck, 2034 .parent = &func_96m_ck,
1661 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2035 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1662 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1663 .enable_bit = 31, 2037 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1664 .recalc = &omap2_followparent_recalc, 2038 .recalc = &followparent_recalc,
1665}; 2039};
1666 2040
1667static struct clk mailboxes_ick = { 2041static struct clk mailboxes_ick = {
1668 .name = "mailboxes_ick", 2042 .name = "mailboxes_ick",
1669 .parent = &l4_ck, 2043 .parent = &l4_ck,
1670 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2044 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1671 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2045 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1672 .enable_bit = 30, 2046 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1673 .recalc = &omap2_followparent_recalc, 2047 .recalc = &followparent_recalc,
1674}; 2048};
1675 2049
1676static struct clk wdt4_ick = { 2050static struct clk wdt4_ick = {
1677 .name = "wdt4_ick", 2051 .name = "wdt4_ick",
1678 .parent = &l4_ck, 2052 .parent = &l4_ck,
1679 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2053 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1680 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2054 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1681 .enable_bit = 29, 2055 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1682 .recalc = &omap2_followparent_recalc, 2056 .recalc = &followparent_recalc,
1683}; 2057};
1684 2058
1685static struct clk wdt4_fck = { 2059static struct clk wdt4_fck = {
1686 .name = "wdt4_fck", 2060 .name = "wdt4_fck",
1687 .parent = &func_32k_ck, 2061 .parent = &func_32k_ck,
1688 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2062 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1689 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2063 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1690 .enable_bit = 29, 2064 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1691 .recalc = &omap2_followparent_recalc, 2065 .recalc = &followparent_recalc,
1692}; 2066};
1693 2067
1694static struct clk wdt3_ick = { 2068static struct clk wdt3_ick = {
1695 .name = "wdt3_ick", 2069 .name = "wdt3_ick",
1696 .parent = &l4_ck, 2070 .parent = &l4_ck,
1697 .flags = CLOCK_IN_OMAP242X, 2071 .flags = CLOCK_IN_OMAP242X,
1698 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1699 .enable_bit = 28, 2073 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1700 .recalc = &omap2_followparent_recalc, 2074 .recalc = &followparent_recalc,
1701}; 2075};
1702 2076
1703static struct clk wdt3_fck = { 2077static struct clk wdt3_fck = {
1704 .name = "wdt3_fck", 2078 .name = "wdt3_fck",
1705 .parent = &func_32k_ck, 2079 .parent = &func_32k_ck,
1706 .flags = CLOCK_IN_OMAP242X, 2080 .flags = CLOCK_IN_OMAP242X,
1707 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2081 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1708 .enable_bit = 28, 2082 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1709 .recalc = &omap2_followparent_recalc, 2083 .recalc = &followparent_recalc,
1710}; 2084};
1711 2085
1712static struct clk mspro_ick = { 2086static struct clk mspro_ick = {
1713 .name = "mspro_ick", 2087 .name = "mspro_ick",
1714 .parent = &l4_ck, 2088 .parent = &l4_ck,
1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2089 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1717 .enable_bit = 27, 2091 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1718 .recalc = &omap2_followparent_recalc, 2092 .recalc = &followparent_recalc,
1719}; 2093};
1720 2094
1721static struct clk mspro_fck = { 2095static struct clk mspro_fck = {
1722 .name = "mspro_fck", 2096 .name = "mspro_fck",
1723 .parent = &func_96m_ck, 2097 .parent = &func_96m_ck,
1724 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1725 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2099 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1726 .enable_bit = 27, 2100 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1727 .recalc = &omap2_followparent_recalc, 2101 .recalc = &followparent_recalc,
1728}; 2102};
1729 2103
1730static struct clk mmc_ick = { 2104static struct clk mmc_ick = {
1731 .name = "mmc_ick", 2105 .name = "mmc_ick",
1732 .parent = &l4_ck, 2106 .parent = &l4_ck,
1733 .flags = CLOCK_IN_OMAP242X, 2107 .flags = CLOCK_IN_OMAP242X,
1734 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2108 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1735 .enable_bit = 26, 2109 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1736 .recalc = &omap2_followparent_recalc, 2110 .recalc = &followparent_recalc,
1737}; 2111};
1738 2112
1739static struct clk mmc_fck = { 2113static struct clk mmc_fck = {
1740 .name = "mmc_fck", 2114 .name = "mmc_fck",
1741 .parent = &func_96m_ck, 2115 .parent = &func_96m_ck,
1742 .flags = CLOCK_IN_OMAP242X, 2116 .flags = CLOCK_IN_OMAP242X,
1743 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2117 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1744 .enable_bit = 26, 2118 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1745 .recalc = &omap2_followparent_recalc, 2119 .recalc = &followparent_recalc,
1746}; 2120};
1747 2121
1748static struct clk fac_ick = { 2122static struct clk fac_ick = {
1749 .name = "fac_ick", 2123 .name = "fac_ick",
1750 .parent = &l4_ck, 2124 .parent = &l4_ck,
1751 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2125 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1752 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2126 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1753 .enable_bit = 25, 2127 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1754 .recalc = &omap2_followparent_recalc, 2128 .recalc = &followparent_recalc,
1755}; 2129};
1756 2130
1757static struct clk fac_fck = { 2131static struct clk fac_fck = {
1758 .name = "fac_fck", 2132 .name = "fac_fck",
1759 .parent = &func_12m_ck, 2133 .parent = &func_12m_ck,
1760 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2134 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1761 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1762 .enable_bit = 25, 2136 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1763 .recalc = &omap2_followparent_recalc, 2137 .recalc = &followparent_recalc,
1764}; 2138};
1765 2139
1766static struct clk eac_ick = { 2140static struct clk eac_ick = {
1767 .name = "eac_ick", 2141 .name = "eac_ick",
1768 .parent = &l4_ck, 2142 .parent = &l4_ck,
1769 .flags = CLOCK_IN_OMAP242X, 2143 .flags = CLOCK_IN_OMAP242X,
1770 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1771 .enable_bit = 24, 2145 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1772 .recalc = &omap2_followparent_recalc, 2146 .recalc = &followparent_recalc,
1773}; 2147};
1774 2148
1775static struct clk eac_fck = { 2149static struct clk eac_fck = {
1776 .name = "eac_fck", 2150 .name = "eac_fck",
1777 .parent = &func_96m_ck, 2151 .parent = &func_96m_ck,
1778 .flags = CLOCK_IN_OMAP242X, 2152 .flags = CLOCK_IN_OMAP242X,
1779 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2153 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1780 .enable_bit = 24, 2154 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1781 .recalc = &omap2_followparent_recalc, 2155 .recalc = &followparent_recalc,
1782}; 2156};
1783 2157
1784static struct clk hdq_ick = { 2158static struct clk hdq_ick = {
1785 .name = "hdq_ick", 2159 .name = "hdq_ick",
1786 .parent = &l4_ck, 2160 .parent = &l4_ck,
1787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2161 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2162 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789 .enable_bit = 23, 2163 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1790 .recalc = &omap2_followparent_recalc, 2164 .recalc = &followparent_recalc,
1791}; 2165};
1792 2166
1793static struct clk hdq_fck = { 2167static struct clk hdq_fck = {
1794 .name = "hdq_fck", 2168 .name = "hdq_fck",
1795 .parent = &func_12m_ck, 2169 .parent = &func_12m_ck,
1796 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2170 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1797 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2171 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1798 .enable_bit = 23, 2172 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1799 .recalc = &omap2_followparent_recalc, 2173 .recalc = &followparent_recalc,
1800}; 2174};
1801 2175
1802static struct clk i2c2_ick = { 2176static struct clk i2c2_ick = {
@@ -1804,28 +2178,29 @@ static struct clk i2c2_ick = {
1804 .id = 2, 2178 .id = 2,
1805 .parent = &l4_ck, 2179 .parent = &l4_ck,
1806 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2180 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1807 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2181 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808 .enable_bit = 20, 2182 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1809 .recalc = &omap2_followparent_recalc, 2183 .recalc = &followparent_recalc,
1810}; 2184};
1811 2185
1812static struct clk i2c2_fck = { 2186static struct clk i2c2_fck = {
1813 .name = "i2c_fck", 2187 .name = "i2c_fck",
1814 .id = 2, 2188 .id = 2,
1815 .parent = &func_12m_ck, 2189 .parent = &func_12m_ck,
1816 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2190 .flags = CLOCK_IN_OMAP242X,
1817 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2191 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1818 .enable_bit = 20, 2192 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1819 .recalc = &omap2_followparent_recalc, 2193 .recalc = &followparent_recalc,
1820}; 2194};
1821 2195
1822static struct clk i2chs2_fck = { 2196static struct clk i2chs2_fck = {
1823 .name = "i2chs2_fck", 2197 .name = "i2chs_fck",
2198 .id = 2,
1824 .parent = &func_96m_ck, 2199 .parent = &func_96m_ck,
1825 .flags = CLOCK_IN_OMAP243X, 2200 .flags = CLOCK_IN_OMAP243X,
1826 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 2201 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1827 .enable_bit = 20, 2202 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1828 .recalc = &omap2_followparent_recalc, 2203 .recalc = &followparent_recalc,
1829}; 2204};
1830 2205
1831static struct clk i2c1_ick = { 2206static struct clk i2c1_ick = {
@@ -1833,202 +2208,260 @@ static struct clk i2c1_ick = {
1833 .id = 1, 2208 .id = 1,
1834 .parent = &l4_ck, 2209 .parent = &l4_ck,
1835 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2210 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1836 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = 19, 2212 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1838 .recalc = &omap2_followparent_recalc, 2213 .recalc = &followparent_recalc,
1839}; 2214};
1840 2215
1841static struct clk i2c1_fck = { 2216static struct clk i2c1_fck = {
1842 .name = "i2c_fck", 2217 .name = "i2c_fck",
1843 .id = 1, 2218 .id = 1,
1844 .parent = &func_12m_ck, 2219 .parent = &func_12m_ck,
1845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2220 .flags = CLOCK_IN_OMAP242X,
1846 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2221 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1847 .enable_bit = 19, 2222 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1848 .recalc = &omap2_followparent_recalc, 2223 .recalc = &followparent_recalc,
1849}; 2224};
1850 2225
1851static struct clk i2chs1_fck = { 2226static struct clk i2chs1_fck = {
1852 .name = "i2chs1_fck", 2227 .name = "i2chs_fck",
2228 .id = 1,
1853 .parent = &func_96m_ck, 2229 .parent = &func_96m_ck,
1854 .flags = CLOCK_IN_OMAP243X, 2230 .flags = CLOCK_IN_OMAP243X,
1855 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 2231 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1856 .enable_bit = 19, 2232 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1857 .recalc = &omap2_followparent_recalc, 2233 .recalc = &followparent_recalc,
2234};
2235
2236static struct clk gpmc_fck = {
2237 .name = "gpmc_fck",
2238 .parent = &core_l3_ck,
2239 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2240 .recalc = &followparent_recalc,
2241};
2242
2243static struct clk sdma_fck = {
2244 .name = "sdma_fck",
2245 .parent = &core_l3_ck,
2246 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2247 .recalc = &followparent_recalc,
2248};
2249
2250static struct clk sdma_ick = {
2251 .name = "sdma_ick",
2252 .parent = &l4_ck,
2253 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2254 .recalc = &followparent_recalc,
1858}; 2255};
1859 2256
1860static struct clk vlynq_ick = { 2257static struct clk vlynq_ick = {
1861 .name = "vlynq_ick", 2258 .name = "vlynq_ick",
1862 .parent = &core_l3_ck, 2259 .parent = &core_l3_ck,
1863 .flags = CLOCK_IN_OMAP242X, 2260 .flags = CLOCK_IN_OMAP242X,
1864 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 2261 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865 .enable_bit = 3, 2262 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1866 .recalc = &omap2_followparent_recalc, 2263 .recalc = &followparent_recalc,
2264};
2265
2266static const struct clksel_rate vlynq_fck_96m_rates[] = {
2267 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2268 { .div = 0 }
2269};
2270
2271static const struct clksel_rate vlynq_fck_core_rates[] = {
2272 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2273 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2274 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2275 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2276 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2277 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2278 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2279 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2280 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2281 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2282 { .div = 0 }
2283};
2284
2285static const struct clksel vlynq_fck_clksel[] = {
2286 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2287 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2288 { .parent = NULL }
1867}; 2289};
1868 2290
1869static struct clk vlynq_fck = { 2291static struct clk vlynq_fck = {
1870 .name = "vlynq_fck", 2292 .name = "vlynq_fck",
1871 .parent = &func_96m_ck, 2293 .parent = &func_96m_ck,
1872 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, 2294 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
1873 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 2295 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1874 .enable_bit = 3, 2296 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1875 .src_offset = 15, 2297 .init = &omap2_init_clksel_parent,
1876 .recalc = &omap2_followparent_recalc, 2298 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2299 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2300 .clksel = vlynq_fck_clksel,
2301 .recalc = &omap2_clksel_recalc,
2302 .round_rate = &omap2_clksel_round_rate,
2303 .set_rate = &omap2_clksel_set_rate
1877}; 2304};
1878 2305
1879static struct clk sdrc_ick = { 2306static struct clk sdrc_ick = {
1880 .name = "sdrc_ick", 2307 .name = "sdrc_ick",
1881 .parent = &l4_ck, 2308 .parent = &l4_ck,
1882 .flags = CLOCK_IN_OMAP243X, 2309 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1883 .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE, 2310 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1884 .enable_bit = 2, 2311 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1885 .recalc = &omap2_followparent_recalc, 2312 .recalc = &followparent_recalc,
1886}; 2313};
1887 2314
1888static struct clk des_ick = { 2315static struct clk des_ick = {
1889 .name = "des_ick", 2316 .name = "des_ick",
1890 .parent = &l4_ck, 2317 .parent = &l4_ck,
1891 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2318 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1892 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, 2319 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1893 .enable_bit = 0, 2320 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1894 .recalc = &omap2_followparent_recalc, 2321 .recalc = &followparent_recalc,
1895}; 2322};
1896 2323
1897static struct clk sha_ick = { 2324static struct clk sha_ick = {
1898 .name = "sha_ick", 2325 .name = "sha_ick",
1899 .parent = &l4_ck, 2326 .parent = &l4_ck,
1900 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2327 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1901 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, 2328 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1902 .enable_bit = 1, 2329 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1903 .recalc = &omap2_followparent_recalc, 2330 .recalc = &followparent_recalc,
1904}; 2331};
1905 2332
1906static struct clk rng_ick = { 2333static struct clk rng_ick = {
1907 .name = "rng_ick", 2334 .name = "rng_ick",
1908 .parent = &l4_ck, 2335 .parent = &l4_ck,
1909 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2336 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1910 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, 2337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1911 .enable_bit = 2, 2338 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1912 .recalc = &omap2_followparent_recalc, 2339 .recalc = &followparent_recalc,
1913}; 2340};
1914 2341
1915static struct clk aes_ick = { 2342static struct clk aes_ick = {
1916 .name = "aes_ick", 2343 .name = "aes_ick",
1917 .parent = &l4_ck, 2344 .parent = &l4_ck,
1918 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2345 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1919 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, 2346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1920 .enable_bit = 3, 2347 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1921 .recalc = &omap2_followparent_recalc, 2348 .recalc = &followparent_recalc,
1922}; 2349};
1923 2350
1924static struct clk pka_ick = { 2351static struct clk pka_ick = {
1925 .name = "pka_ick", 2352 .name = "pka_ick",
1926 .parent = &l4_ck, 2353 .parent = &l4_ck,
1927 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2354 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1928 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, 2355 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1929 .enable_bit = 4, 2356 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1930 .recalc = &omap2_followparent_recalc, 2357 .recalc = &followparent_recalc,
1931}; 2358};
1932 2359
1933static struct clk usb_fck = { 2360static struct clk usb_fck = {
1934 .name = "usb_fck", 2361 .name = "usb_fck",
1935 .parent = &func_48m_ck, 2362 .parent = &func_48m_ck,
1936 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2363 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1937 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 2364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1938 .enable_bit = 0, 2365 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1939 .recalc = &omap2_followparent_recalc, 2366 .recalc = &followparent_recalc,
1940}; 2367};
1941 2368
1942static struct clk usbhs_ick = { 2369static struct clk usbhs_ick = {
1943 .name = "usbhs_ick", 2370 .name = "usbhs_ick",
1944 .parent = &core_l3_ck, 2371 .parent = &core_l3_ck,
1945 .flags = CLOCK_IN_OMAP243X, 2372 .flags = CLOCK_IN_OMAP243X,
1946 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 2373 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1947 .enable_bit = 6, 2374 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1948 .recalc = &omap2_followparent_recalc, 2375 .recalc = &followparent_recalc,
1949}; 2376};
1950 2377
1951static struct clk mmchs1_ick = { 2378static struct clk mmchs1_ick = {
1952 .name = "mmchs1_ick", 2379 .name = "mmchs_ick",
2380 .id = 1,
1953 .parent = &l4_ck, 2381 .parent = &l4_ck,
1954 .flags = CLOCK_IN_OMAP243X, 2382 .flags = CLOCK_IN_OMAP243X,
1955 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 2383 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1956 .enable_bit = 7, 2384 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1957 .recalc = &omap2_followparent_recalc, 2385 .recalc = &followparent_recalc,
1958}; 2386};
1959 2387
1960static struct clk mmchs1_fck = { 2388static struct clk mmchs1_fck = {
1961 .name = "mmchs1_fck", 2389 .name = "mmchs_fck",
2390 .id = 1,
1962 .parent = &func_96m_ck, 2391 .parent = &func_96m_ck,
1963 .flags = CLOCK_IN_OMAP243X, 2392 .flags = CLOCK_IN_OMAP243X,
1964 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 2393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1965 .enable_bit = 7, 2394 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1966 .recalc = &omap2_followparent_recalc, 2395 .recalc = &followparent_recalc,
1967}; 2396};
1968 2397
1969static struct clk mmchs2_ick = { 2398static struct clk mmchs2_ick = {
1970 .name = "mmchs2_ick", 2399 .name = "mmchs_ick",
2400 .id = 2,
1971 .parent = &l4_ck, 2401 .parent = &l4_ck,
1972 .flags = CLOCK_IN_OMAP243X, 2402 .flags = CLOCK_IN_OMAP243X,
1973 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 2403 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1974 .enable_bit = 8, 2404 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1975 .recalc = &omap2_followparent_recalc, 2405 .recalc = &followparent_recalc,
1976}; 2406};
1977 2407
1978static struct clk mmchs2_fck = { 2408static struct clk mmchs2_fck = {
1979 .name = "mmchs2_fck", 2409 .name = "mmchs_fck",
2410 .id = 2,
1980 .parent = &func_96m_ck, 2411 .parent = &func_96m_ck,
1981 .flags = CLOCK_IN_OMAP243X, 2412 .flags = CLOCK_IN_OMAP243X,
1982 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 2413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1983 .enable_bit = 8, 2414 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1984 .recalc = &omap2_followparent_recalc, 2415 .recalc = &followparent_recalc,
1985}; 2416};
1986 2417
1987static struct clk gpio5_ick = { 2418static struct clk gpio5_ick = {
1988 .name = "gpio5_ick", 2419 .name = "gpio5_ick",
1989 .parent = &l4_ck, 2420 .parent = &l4_ck,
1990 .flags = CLOCK_IN_OMAP243X, 2421 .flags = CLOCK_IN_OMAP243X,
1991 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 2422 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1992 .enable_bit = 10, 2423 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1993 .recalc = &omap2_followparent_recalc, 2424 .recalc = &followparent_recalc,
1994}; 2425};
1995 2426
1996static struct clk gpio5_fck = { 2427static struct clk gpio5_fck = {
1997 .name = "gpio5_fck", 2428 .name = "gpio5_fck",
1998 .parent = &func_32k_ck, 2429 .parent = &func_32k_ck,
1999 .flags = CLOCK_IN_OMAP243X, 2430 .flags = CLOCK_IN_OMAP243X,
2000 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 2431 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2001 .enable_bit = 10, 2432 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2002 .recalc = &omap2_followparent_recalc, 2433 .recalc = &followparent_recalc,
2003}; 2434};
2004 2435
2005static struct clk mdm_intc_ick = { 2436static struct clk mdm_intc_ick = {
2006 .name = "mdm_intc_ick", 2437 .name = "mdm_intc_ick",
2007 .parent = &l4_ck, 2438 .parent = &l4_ck,
2008 .flags = CLOCK_IN_OMAP243X, 2439 .flags = CLOCK_IN_OMAP243X,
2009 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 2440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2010 .enable_bit = 11, 2441 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2011 .recalc = &omap2_followparent_recalc, 2442 .recalc = &followparent_recalc,
2012}; 2443};
2013 2444
2014static struct clk mmchsdb1_fck = { 2445static struct clk mmchsdb1_fck = {
2015 .name = "mmchsdb1_fck", 2446 .name = "mmchsdb_fck",
2447 .id = 1,
2016 .parent = &func_32k_ck, 2448 .parent = &func_32k_ck,
2017 .flags = CLOCK_IN_OMAP243X, 2449 .flags = CLOCK_IN_OMAP243X,
2018 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 2450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2019 .enable_bit = 16, 2451 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2020 .recalc = &omap2_followparent_recalc, 2452 .recalc = &followparent_recalc,
2021}; 2453};
2022 2454
2023static struct clk mmchsdb2_fck = { 2455static struct clk mmchsdb2_fck = {
2024 .name = "mmchsdb2_fck", 2456 .name = "mmchsdb_fck",
2457 .id = 2,
2025 .parent = &func_32k_ck, 2458 .parent = &func_32k_ck,
2026 .flags = CLOCK_IN_OMAP243X, 2459 .flags = CLOCK_IN_OMAP243X,
2027 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 2460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2028 .enable_bit = 17, 2461 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2029 .recalc = &omap2_followparent_recalc, 2462 .recalc = &followparent_recalc,
2030}; 2463};
2031#endif /* OLD_CK */ 2464
2032/* 2465/*
2033 * This clock is a composite clock which does entire set changes then 2466 * This clock is a composite clock which does entire set changes then
2034 * forces a rebalance. It keys on the MPU speed, but it really could 2467 * forces a rebalance. It keys on the MPU speed, but it really could
@@ -2048,11 +2481,12 @@ static struct clk virt_prcm_set = {
2048 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2481 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2049 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, 2482 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2050 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ 2483 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2484 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2051 .set_rate = &omap2_select_table_rate, 2485 .set_rate = &omap2_select_table_rate,
2052 .round_rate = &omap2_round_to_table_rate, 2486 .round_rate = &omap2_round_to_table_rate,
2053}; 2487};
2054#ifdef OLD_CK 2488
2055static struct clk *onchip_clks[] = { 2489static struct clk *onchip_24xx_clks[] __initdata = {
2056 /* external root sources */ 2490 /* external root sources */
2057 &func_32k_ck, 2491 &func_32k_ck,
2058 &osc_ck, 2492 &osc_ck,
@@ -2065,23 +2499,24 @@ static struct clk *onchip_clks[] = {
2065 /* internal prcm root sources */ 2499 /* internal prcm root sources */
2066 &func_54m_ck, 2500 &func_54m_ck,
2067 &core_ck, 2501 &core_ck,
2068 &sleep_ck,
2069 &func_96m_ck, 2502 &func_96m_ck,
2070 &func_48m_ck, 2503 &func_48m_ck,
2071 &func_12m_ck, 2504 &func_12m_ck,
2072 &wdt1_osc_ck, 2505 &wdt1_osc_ck,
2506 &sys_clkout_src,
2073 &sys_clkout, 2507 &sys_clkout,
2508 &sys_clkout2_src,
2074 &sys_clkout2, 2509 &sys_clkout2,
2075 &emul_ck, 2510 &emul_ck,
2076 /* mpu domain clocks */ 2511 /* mpu domain clocks */
2077 &mpu_ck, 2512 &mpu_ck,
2078 /* dsp domain clocks */ 2513 /* dsp domain clocks */
2079 &iva2_1_fck, /* 2430 */
2080 &iva2_1_ick,
2081 &dsp_ick, /* 2420 */
2082 &dsp_fck, 2514 &dsp_fck,
2083 &iva1_ifck, 2515 &dsp_irate_ick,
2084 &iva1_mpu_int_ifck, 2516 &dsp_ick, /* 242x */
2517 &iva2_1_ick, /* 243x */
2518 &iva1_ifck, /* 242x */
2519 &iva1_mpu_int_ifck, /* 242x */
2085 /* GFX domain clocks */ 2520 /* GFX domain clocks */
2086 &gfx_3d_fck, 2521 &gfx_3d_fck,
2087 &gfx_2d_fck, 2522 &gfx_2d_fck,
@@ -2181,6 +2616,9 @@ static struct clk *onchip_clks[] = {
2181 &i2c2_ick, 2616 &i2c2_ick,
2182 &i2c2_fck, 2617 &i2c2_fck,
2183 &i2chs2_fck, 2618 &i2chs2_fck,
2619 &gpmc_fck,
2620 &sdma_fck,
2621 &sdma_ick,
2184 &vlynq_ick, 2622 &vlynq_ick,
2185 &vlynq_fck, 2623 &vlynq_fck,
2186 &sdrc_ick, 2624 &sdrc_ick,
@@ -2201,17 +2639,6 @@ static struct clk *onchip_clks[] = {
2201 &mmchsdb1_fck, 2639 &mmchsdb1_fck,
2202 &mmchsdb2_fck, 2640 &mmchsdb2_fck,
2203}; 2641};
2204#endif /* OLD_CK */
2205
2206static struct clk *onchip_24xx_clks[] __initdata = {
2207 /* external root sources */
2208 &osc_ck,
2209 &sys_ck,
2210 /* internal analog sources */
2211 &dpll_ck,
2212 &apll96_ck,
2213 &apll54_ck,
2214};
2215 2642
2216#endif 2643#endif
2217 2644
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 03:25:49 -0400