diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-01-31 05:05:51 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 12:50:42 -0500 |
commit | 3f0a820c4c0b4670fb5f164baa5582e23c2ef118 (patch) | |
tree | 6af02e1456c0316791ab95e7da9c09496f29c232 /arch/arm/mach-omap2/clock24xx.h | |
parent | b5088c0d90b898802318c62caf2320a53df6ce57 (diff) |
[ARM] omap: create a proper tree of clocks
Traditionally, we've tracked the parent/child relationships between
clk structures by setting the child's parent member to point at the
upstream clock. As a result, when decending the tree, we have had
to scan all clocks to find the children.
Avoid this wasteful scanning by keeping a list of the clock's children.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock24xx.h')
-rw-r--r-- | arch/arm/mach-omap2/clock24xx.h | 28 |
1 files changed, 9 insertions, 19 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 7731ab6acd18..759489822ee9 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h | |||
@@ -621,7 +621,7 @@ static struct clk func_32k_ck = { | |||
621 | .name = "func_32k_ck", | 621 | .name = "func_32k_ck", |
622 | .ops = &clkops_null, | 622 | .ops = &clkops_null, |
623 | .rate = 32000, | 623 | .rate = 32000, |
624 | .flags = RATE_FIXED | RATE_PROPAGATES, | 624 | .flags = RATE_FIXED, |
625 | .clkdm_name = "wkup_clkdm", | 625 | .clkdm_name = "wkup_clkdm", |
626 | }; | 626 | }; |
627 | 627 | ||
@@ -629,7 +629,6 @@ static struct clk func_32k_ck = { | |||
629 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | 629 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
630 | .name = "osc_ck", | 630 | .name = "osc_ck", |
631 | .ops = &clkops_oscck, | 631 | .ops = &clkops_oscck, |
632 | .flags = RATE_PROPAGATES, | ||
633 | .clkdm_name = "wkup_clkdm", | 632 | .clkdm_name = "wkup_clkdm", |
634 | .recalc = &omap2_osc_clk_recalc, | 633 | .recalc = &omap2_osc_clk_recalc, |
635 | }; | 634 | }; |
@@ -639,7 +638,6 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | |||
639 | .name = "sys_ck", /* ~ ref_clk also */ | 638 | .name = "sys_ck", /* ~ ref_clk also */ |
640 | .ops = &clkops_null, | 639 | .ops = &clkops_null, |
641 | .parent = &osc_ck, | 640 | .parent = &osc_ck, |
642 | .flags = RATE_PROPAGATES, | ||
643 | .clkdm_name = "wkup_clkdm", | 641 | .clkdm_name = "wkup_clkdm", |
644 | .recalc = &omap2_sys_clk_recalc, | 642 | .recalc = &omap2_sys_clk_recalc, |
645 | }; | 643 | }; |
@@ -648,7 +646,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | |||
648 | .name = "alt_ck", | 646 | .name = "alt_ck", |
649 | .ops = &clkops_null, | 647 | .ops = &clkops_null, |
650 | .rate = 54000000, | 648 | .rate = 54000000, |
651 | .flags = RATE_FIXED | RATE_PROPAGATES, | 649 | .flags = RATE_FIXED, |
652 | .clkdm_name = "wkup_clkdm", | 650 | .clkdm_name = "wkup_clkdm", |
653 | }; | 651 | }; |
654 | 652 | ||
@@ -680,7 +678,6 @@ static struct clk dpll_ck = { | |||
680 | .ops = &clkops_null, | 678 | .ops = &clkops_null, |
681 | .parent = &sys_ck, /* Can be func_32k also */ | 679 | .parent = &sys_ck, /* Can be func_32k also */ |
682 | .dpll_data = &dpll_dd, | 680 | .dpll_data = &dpll_dd, |
683 | .flags = RATE_PROPAGATES, | ||
684 | .clkdm_name = "wkup_clkdm", | 681 | .clkdm_name = "wkup_clkdm", |
685 | .recalc = &omap2_dpllcore_recalc, | 682 | .recalc = &omap2_dpllcore_recalc, |
686 | .set_rate = &omap2_reprogram_dpllcore, | 683 | .set_rate = &omap2_reprogram_dpllcore, |
@@ -691,7 +688,7 @@ static struct clk apll96_ck = { | |||
691 | .ops = &clkops_fixed, | 688 | .ops = &clkops_fixed, |
692 | .parent = &sys_ck, | 689 | .parent = &sys_ck, |
693 | .rate = 96000000, | 690 | .rate = 96000000, |
694 | .flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | 691 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
695 | .clkdm_name = "wkup_clkdm", | 692 | .clkdm_name = "wkup_clkdm", |
696 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 693 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
697 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | 694 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
@@ -702,7 +699,7 @@ static struct clk apll54_ck = { | |||
702 | .ops = &clkops_fixed, | 699 | .ops = &clkops_fixed, |
703 | .parent = &sys_ck, | 700 | .parent = &sys_ck, |
704 | .rate = 54000000, | 701 | .rate = 54000000, |
705 | .flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | 702 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
706 | .clkdm_name = "wkup_clkdm", | 703 | .clkdm_name = "wkup_clkdm", |
707 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 704 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
708 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | 705 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
@@ -734,7 +731,6 @@ static struct clk func_54m_ck = { | |||
734 | .name = "func_54m_ck", | 731 | .name = "func_54m_ck", |
735 | .ops = &clkops_null, | 732 | .ops = &clkops_null, |
736 | .parent = &apll54_ck, /* can also be alt_clk */ | 733 | .parent = &apll54_ck, /* can also be alt_clk */ |
737 | .flags = RATE_PROPAGATES, | ||
738 | .clkdm_name = "wkup_clkdm", | 734 | .clkdm_name = "wkup_clkdm", |
739 | .init = &omap2_init_clksel_parent, | 735 | .init = &omap2_init_clksel_parent, |
740 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 736 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
@@ -747,7 +743,6 @@ static struct clk core_ck = { | |||
747 | .name = "core_ck", | 743 | .name = "core_ck", |
748 | .ops = &clkops_null, | 744 | .ops = &clkops_null, |
749 | .parent = &dpll_ck, /* can also be 32k */ | 745 | .parent = &dpll_ck, /* can also be 32k */ |
750 | .flags = RATE_PROPAGATES, | ||
751 | .clkdm_name = "wkup_clkdm", | 746 | .clkdm_name = "wkup_clkdm", |
752 | .recalc = &followparent_recalc, | 747 | .recalc = &followparent_recalc, |
753 | }; | 748 | }; |
@@ -774,7 +769,6 @@ static struct clk func_96m_ck = { | |||
774 | .name = "func_96m_ck", | 769 | .name = "func_96m_ck", |
775 | .ops = &clkops_null, | 770 | .ops = &clkops_null, |
776 | .parent = &apll96_ck, | 771 | .parent = &apll96_ck, |
777 | .flags = RATE_PROPAGATES, | ||
778 | .clkdm_name = "wkup_clkdm", | 772 | .clkdm_name = "wkup_clkdm", |
779 | .init = &omap2_init_clksel_parent, | 773 | .init = &omap2_init_clksel_parent, |
780 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 774 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
@@ -807,7 +801,6 @@ static struct clk func_48m_ck = { | |||
807 | .name = "func_48m_ck", | 801 | .name = "func_48m_ck", |
808 | .ops = &clkops_null, | 802 | .ops = &clkops_null, |
809 | .parent = &apll96_ck, /* 96M or Alt */ | 803 | .parent = &apll96_ck, /* 96M or Alt */ |
810 | .flags = RATE_PROPAGATES, | ||
811 | .clkdm_name = "wkup_clkdm", | 804 | .clkdm_name = "wkup_clkdm", |
812 | .init = &omap2_init_clksel_parent, | 805 | .init = &omap2_init_clksel_parent, |
813 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 806 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
@@ -823,7 +816,6 @@ static struct clk func_12m_ck = { | |||
823 | .ops = &clkops_null, | 816 | .ops = &clkops_null, |
824 | .parent = &func_48m_ck, | 817 | .parent = &func_48m_ck, |
825 | .fixed_div = 4, | 818 | .fixed_div = 4, |
826 | .flags = RATE_PROPAGATES, | ||
827 | .clkdm_name = "wkup_clkdm", | 819 | .clkdm_name = "wkup_clkdm", |
828 | .recalc = &omap2_fixed_divisor_recalc, | 820 | .recalc = &omap2_fixed_divisor_recalc, |
829 | }; | 821 | }; |
@@ -876,7 +868,6 @@ static struct clk sys_clkout_src = { | |||
876 | .name = "sys_clkout_src", | 868 | .name = "sys_clkout_src", |
877 | .ops = &clkops_omap2_dflt, | 869 | .ops = &clkops_omap2_dflt, |
878 | .parent = &func_54m_ck, | 870 | .parent = &func_54m_ck, |
879 | .flags = RATE_PROPAGATES, | ||
880 | .clkdm_name = "wkup_clkdm", | 871 | .clkdm_name = "wkup_clkdm", |
881 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 872 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
882 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | 873 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
@@ -921,7 +912,6 @@ static struct clk sys_clkout2_src = { | |||
921 | .name = "sys_clkout2_src", | 912 | .name = "sys_clkout2_src", |
922 | .ops = &clkops_omap2_dflt, | 913 | .ops = &clkops_omap2_dflt, |
923 | .parent = &func_54m_ck, | 914 | .parent = &func_54m_ck, |
924 | .flags = RATE_PROPAGATES, | ||
925 | .clkdm_name = "wkup_clkdm", | 915 | .clkdm_name = "wkup_clkdm", |
926 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 916 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
927 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | 917 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
@@ -992,7 +982,7 @@ static struct clk mpu_ck = { /* Control cpu */ | |||
992 | .name = "mpu_ck", | 982 | .name = "mpu_ck", |
993 | .ops = &clkops_null, | 983 | .ops = &clkops_null, |
994 | .parent = &core_ck, | 984 | .parent = &core_ck, |
995 | .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, | 985 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
996 | .clkdm_name = "mpu_clkdm", | 986 | .clkdm_name = "mpu_clkdm", |
997 | .init = &omap2_init_clksel_parent, | 987 | .init = &omap2_init_clksel_parent, |
998 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | 988 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
@@ -1034,7 +1024,7 @@ static struct clk dsp_fck = { | |||
1034 | .name = "dsp_fck", | 1024 | .name = "dsp_fck", |
1035 | .ops = &clkops_omap2_dflt_wait, | 1025 | .ops = &clkops_omap2_dflt_wait, |
1036 | .parent = &core_ck, | 1026 | .parent = &core_ck, |
1037 | .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, | 1027 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
1038 | .clkdm_name = "dsp_clkdm", | 1028 | .clkdm_name = "dsp_clkdm", |
1039 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1029 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
1040 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 1030 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
@@ -1102,7 +1092,7 @@ static struct clk iva1_ifck = { | |||
1102 | .name = "iva1_ifck", | 1092 | .name = "iva1_ifck", |
1103 | .ops = &clkops_omap2_dflt_wait, | 1093 | .ops = &clkops_omap2_dflt_wait, |
1104 | .parent = &core_ck, | 1094 | .parent = &core_ck, |
1105 | .flags = CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, | 1095 | .flags = CONFIG_PARTICIPANT | DELAYED_APP, |
1106 | .clkdm_name = "iva1_clkdm", | 1096 | .clkdm_name = "iva1_clkdm", |
1107 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1097 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
1108 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | 1098 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, |
@@ -1165,7 +1155,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | |||
1165 | .name = "core_l3_ck", | 1155 | .name = "core_l3_ck", |
1166 | .ops = &clkops_null, | 1156 | .ops = &clkops_null, |
1167 | .parent = &core_ck, | 1157 | .parent = &core_ck, |
1168 | .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, | 1158 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
1169 | .clkdm_name = "core_l3_clkdm", | 1159 | .clkdm_name = "core_l3_clkdm", |
1170 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1160 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
1171 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | 1161 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
@@ -1227,7 +1217,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */ | |||
1227 | .name = "l4_ck", | 1217 | .name = "l4_ck", |
1228 | .ops = &clkops_null, | 1218 | .ops = &clkops_null, |
1229 | .parent = &core_l3_ck, | 1219 | .parent = &core_l3_ck, |
1230 | .flags = DELAYED_APP | RATE_PROPAGATES, | 1220 | .flags = DELAYED_APP, |
1231 | .clkdm_name = "core_l4_clkdm", | 1221 | .clkdm_name = "core_l4_clkdm", |
1232 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1222 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
1233 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | 1223 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |