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authorPaul Walmsley <paul@pwsan.com>2012-09-16 12:45:54 -0400
committerPaul Walmsley <paul@pwsan.com>2012-11-12 21:10:20 -0500
commit8c725dcd2246e8500a6fdd394ef4cb0cf96f2217 (patch)
treec46911dd42206d678e4a7fc8a2f22101999baaa9 /arch/arm/mach-omap2/clock.h
parentb6827ad5b6a30771dafa2fa8493594e56ca87d5d (diff)
ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h
Define four convenience macros to be used in the upcoming OMAP2+ common clock framework port. Although the use of these macros will make the data somewhat more difficult to read, they significantly reduce the number of lines in the output patch data. Most of these were created by Rajendra Nayak and Mike Turquette, as far as I know. Signed-off-by: Paul Walmsley <paul@pwsan.com> [mturquette@ti.com: added DEFINE_CLK_OMAP_HSDIVIDER macro] Signed-off-by: Mike Turquette <mturquette@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.h')
-rw-r--r--arch/arm/mach-omap2/clock.h77
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index e669fc839859..ec63f015e60e 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -58,6 +58,83 @@ struct omap_clk {
58struct clockdomain; 58struct clockdomain;
59#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 59#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
60 60
61#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
62 static struct clk _name = { \
63 .name = #_name, \
64 .hw = &_name##_hw.hw, \
65 .parent_names = _parent_array_name, \
66 .num_parents = ARRAY_SIZE(_parent_array_name), \
67 .ops = &_clkops_name, \
68 };
69
70#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
71 static struct clk_hw_omap _name##_hw = { \
72 .hw = { \
73 .clk = &_name, \
74 }, \
75 .clkdm_name = _clkdm_name, \
76 };
77
78#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
79 _clksel_reg, _clksel_mask, \
80 _parent_names, _ops) \
81 static struct clk _name; \
82 static struct clk_hw_omap _name##_hw = { \
83 .hw = { \
84 .clk = &_name, \
85 }, \
86 .clksel = _clksel, \
87 .clksel_reg = _clksel_reg, \
88 .clksel_mask = _clksel_mask, \
89 .clkdm_name = _clkdm_name, \
90 }; \
91 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
92
93#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
94 _clksel_reg, _clksel_mask, \
95 _enable_reg, _enable_bit, \
96 _hwops, _parent_names, _ops) \
97 static struct clk _name; \
98 static struct clk_hw_omap _name##_hw = { \
99 .hw = { \
100 .clk = &_name, \
101 }, \
102 .ops = _hwops, \
103 .enable_reg = _enable_reg, \
104 .enable_bit = _enable_bit, \
105 .clksel = _clksel, \
106 .clksel_reg = _clksel_reg, \
107 .clksel_mask = _clksel_mask, \
108 .clkdm_name = _clkdm_name, \
109 }; \
110 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
111
112#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
113 _parent_ptr, _flags, \
114 _clksel_reg, _clksel_mask) \
115 static const struct clksel _name##_div[] = { \
116 { \
117 .parent = _parent_ptr, \
118 .rates = div31_1to31_rates \
119 }, \
120 { .parent = NULL }, \
121 }; \
122 static struct clk _name; \
123 static const char *_name##_parent_names[] = { \
124 _parent_name, \
125 }; \
126 static struct clk_hw_omap _name##_hw = { \
127 .hw = { \
128 .clk = &_name, \
129 }, \
130 .clksel = _name##_div, \
131 .clksel_reg = _clksel_reg, \
132 .clksel_mask = _clksel_mask, \
133 .ops = &clkhwops_omap4_dpllmx, \
134 }; \
135 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
136
137
61#else 138#else
62 139
63struct module; 140struct module;