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authorRichard Woodruff <r-woodruff2@ti.com>2007-01-26 15:08:51 -0500
committerTony Lindgren <tony@atomide.com>2007-03-07 04:17:46 -0500
commit474844f7083b2381db9b3523dc6de9108fc4c732 (patch)
tree741f4876844157876698a446f22ff83be72acfb7 /arch/arm/mach-omap2/clock.h
parente6da2aa74ac878ebc5b49c42a0ee94a69884b9af (diff)
ARM: OMAP: Fix OMAP2 dss2 so clk_set_parent works
This adds the delayed application attribute to the dss2 clock. DSS2 can't select the 48MHz APLL with properly with out validating the configuration as trigged by this flag. Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.h')
-rw-r--r--arch/arm/mach-omap2/clock.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 8816f5a33a28..162978fd5359 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1013,7 +1013,8 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
1013 .name = "dss2_fck", 1013 .name = "dss2_fck",
1014 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1014 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1015 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1015 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1016 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED, 1016 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1017 DELAYED_APP,
1017 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1018 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1018 .enable_bit = 1, 1019 .enable_bit = 1,
1019 .src_offset = 13, 1020 .src_offset = 13,