diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-06-29 11:23:47 -0400 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-29 11:23:47 -0400 |
commit | a144a5633c1e625c3134c2ce8d549a054468fd98 (patch) | |
tree | 3dcb1d6821ee465bb804c786b59c6dabc5c61da1 /arch/arm/mach-omap2/clock.c | |
parent | 8fc5ffa063f6551c9e6dd66cab89c46ad41e59c5 (diff) | |
parent | 3cbc96050b02d8e5764bd0970067ef294737e324 (diff) |
Merge omap tree
* master.kernel.org:/pub/scm/linux/kernel/git/tmlind/linux-omap-upstream: (26 commits)
ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
ARM: OMAP: Update dmtimers
ARM: OMAP: Make clock variables static
ARM: OMAP: Fix GPMC compilation when DEBUG is defined
ARM: OMAP: Mux updates for external DMA and GPIO
ARM: OMAP: Add OMAP_TAG_CAMERA_SENSOR
ARM: OMAP: Add initial 24xx suspend support
ARM: OMAP: Update cpufreq support for 24xx
ARM: OMAP: Add GPMC support for OMAP2
ARM: OMAP: Fix DMA channel irq handling for omap24xx
ARM: OMAP: OMAP2 DMA burst support
ARM: OMAP: Fix 32 kHz timer and modify GP timer to use GPT1
ARM: OMAP: Port dmtimers to OMAP2 and implement PWM support
ARM: OMAP: Correct two bugs in arch/arm/mach-omap2/clock.c
ARM: OMAP: Register the 24xx McSPI device
ARM: OMAP: Add bitbank SPI driver for Innovator 1510 touchscreen
ARM: OMAP: Aic23 alsa platform driver code for board-innovator
ARM: OMAP: Fix GPIO IRQ mask handling
ARM: OMAP: DMA transfer parameter configuration fix
...
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 72eb4bf571ac..6789dd4029a1 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -660,26 +660,35 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
660 | 660 | ||
661 | /* Isolate control register */ | 661 | /* Isolate control register */ |
662 | div_sel = (SRC_RATE_SEL_MASK & clk->flags); | 662 | div_sel = (SRC_RATE_SEL_MASK & clk->flags); |
663 | div_off = clk->src_offset; | 663 | div_off = clk->rate_offset; |
664 | 664 | ||
665 | validrate = omap2_clksel_round_rate(clk, rate, &new_div); | 665 | validrate = omap2_clksel_round_rate(clk, rate, &new_div); |
666 | if(validrate != rate) | 666 | if (validrate != rate) |
667 | return(ret); | 667 | return(ret); |
668 | 668 | ||
669 | field_val = omap2_get_clksel(&div_sel, &field_mask, clk); | 669 | field_val = omap2_get_clksel(&div_sel, &field_mask, clk); |
670 | if (div_sel == 0) | 670 | if (div_sel == 0) |
671 | return ret; | 671 | return ret; |
672 | 672 | ||
673 | if(clk->flags & CM_SYSCLKOUT_SEL1){ | 673 | if (clk->flags & CM_SYSCLKOUT_SEL1) { |
674 | switch(new_div){ | 674 | switch (new_div) { |
675 | case 16: field_val = 4; break; | 675 | case 16: |
676 | case 8: field_val = 3; break; | 676 | field_val = 4; |
677 | case 4: field_val = 2; break; | 677 | break; |
678 | case 2: field_val = 1; break; | 678 | case 8: |
679 | case 1: field_val = 0; break; | 679 | field_val = 3; |
680 | break; | ||
681 | case 4: | ||
682 | field_val = 2; | ||
683 | break; | ||
684 | case 2: | ||
685 | field_val = 1; | ||
686 | break; | ||
687 | case 1: | ||
688 | field_val = 0; | ||
689 | break; | ||
680 | } | 690 | } |
681 | } | 691 | } else |
682 | else | ||
683 | field_val = new_div; | 692 | field_val = new_div; |
684 | 693 | ||
685 | reg = (void __iomem *)div_sel; | 694 | reg = (void __iomem *)div_sel; |
@@ -744,7 +753,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, | |||
744 | val = 0x2; | 753 | val = 0x2; |
745 | break; | 754 | break; |
746 | case CM_WKUP_SEL1: | 755 | case CM_WKUP_SEL1: |
747 | src_reg_addr = (u32)&CM_CLKSEL2_CORE; | 756 | src_reg_addr = (u32)&CM_CLKSEL_WKUP; |
748 | mask = 0x3; | 757 | mask = 0x3; |
749 | if (src_clk == &func_32k_ck) | 758 | if (src_clk == &func_32k_ck) |
750 | val = 0x0; | 759 | val = 0x0; |
@@ -784,9 +793,9 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, | |||
784 | val = 0; | 793 | val = 0; |
785 | if (src_clk == &sys_ck) | 794 | if (src_clk == &sys_ck) |
786 | val = 1; | 795 | val = 1; |
787 | if (src_clk == &func_54m_ck) | ||
788 | val = 2; | ||
789 | if (src_clk == &func_96m_ck) | 796 | if (src_clk == &func_96m_ck) |
797 | val = 2; | ||
798 | if (src_clk == &func_54m_ck) | ||
790 | val = 3; | 799 | val = 3; |
791 | break; | 800 | break; |
792 | } | 801 | } |