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authorPaul Walmsley <paul@pwsan.com>2010-02-23 00:09:36 -0500
committerPaul Walmsley <paul@pwsan.com>2010-02-24 19:45:15 -0500
commit4d30e82c26b7212021b9a5ab57760d9b8a3075fe (patch)
treeb824e735401ccf62eb762db68d06c4bd3231fab5 /arch/arm/mach-omap2/clock.c
parentad9561609c41f704fd82facd37127e957bcaea94 (diff)
OMAP2/3 clock: combine OMAP2 & 3 boot-time MPU rate change code
The OMAP2 and OMAP3 boot-time MPU rate change code is almost identical. Merge them into mach-omap2/clock.c, and add kerneldoc documentation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
-rw-r--r--arch/arm/mach-omap2/clock.c85
1 files changed, 85 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 426d76f564e7..d1f115d0edad 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -17,6 +17,8 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/errno.h> 19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/delay.h>
20#include <linux/clk.h> 22#include <linux/clk.h>
21#include <linux/io.h> 23#include <linux/io.h>
22#include <linux/bitops.h> 24#include <linux/bitops.h>
@@ -349,6 +351,89 @@ void omap2_clk_disable_unused(struct clk *clk)
349} 351}
350#endif 352#endif
351 353
354/**
355 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
356 * @mpurate_ck_name: clk name of the clock to change rate
357 *
358 * Change the ARM MPU clock rate to the rate specified on the command
359 * line, if one was specified. @mpurate_ck_name should be
360 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
361 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
362 * handled by the virt_prcm_set clock, but this should be handled by
363 * the OPP layer. XXX This is intended to be handled by the OPP layer
364 * code in the near future and should be removed from the clock code.
365 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
366 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
367 * cannot be found, or 0 upon success.
368 */
369int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
370{
371 struct clk *mpurate_ck;
372 int r;
373
374 if (!mpurate)
375 return -EINVAL;
376
377 mpurate_ck = clk_get(NULL, mpurate_ck_name);
378 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
379 return -ENOENT;
380
381 r = clk_set_rate(mpurate_ck, mpurate);
382 if (IS_ERR_VALUE(r)) {
383 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
384 mpurate_ck->name, mpurate, r);
385 return -EINVAL;
386 }
387
388 calibrate_delay();
389 recalculate_root_clocks();
390
391 clk_put(mpurate_ck);
392
393 return 0;
394}
395
396/**
397 * omap2_clk_print_new_rates - print summary of current clock tree rates
398 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
399 * @core_ck_name: clk name for the on-chip CORE_CLK
400 * @mpu_ck_name: clk name for the ARM MPU clock
401 *
402 * Prints a short message to the console with the HFCLKIN oscillator
403 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
404 * Called by the boot-time MPU rate switching code. XXX This is intended
405 * to be handled by the OPP layer code in the near future and should be
406 * removed from the clock code. No return value.
407 */
408void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
409 const char *core_ck_name,
410 const char *mpu_ck_name)
411{
412 struct clk *hfclkin_ck, *core_ck, *mpu_ck;
413 unsigned long hfclkin_rate;
414
415 mpu_ck = clk_get(NULL, mpu_ck_name);
416 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
417 return;
418
419 core_ck = clk_get(NULL, core_ck_name);
420 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
421 return;
422
423 hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
424 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
425 return;
426
427 hfclkin_rate = clk_get_rate(hfclkin_ck);
428
429 pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
430 "%ld.%01ld/%ld/%ld MHz\n",
431 (hfclkin_rate / 1000000),
432 ((hfclkin_rate / 100000) % 10),
433 (clk_get_rate(core_ck) / 1000000),
434 (clk_get_rate(mpu_ck) / 1000000));
435}
436
352/* Common data */ 437/* Common data */
353 438
354struct clk_functions omap2_clk_functions = { 439struct clk_functions omap2_clk_functions = {