Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
  [ARM] 3541/2: workaround for PXA27x erratum E7
  [ARM] nommu: provide a way for correct control register value selection
  [ARM] 3705/1: add supersection support to ioremap()
  [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
  [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
  [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
  [ARM] 3703/1: Add help description for ARCH_EP80219
  [ARM] 3678/1: MMC: Make OMAP MMC work
  [ARM] 3677/1: OMAP: Update H2 defconfig
  [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
  [ARM] Add section support to ioremap
  [ARM] Fix sa11x0 SDRAM selection
  [ARM] Set bit 4 on section mappings correctly depending on CPU
  [ARM] 3666/1: TRIZEPS4 [1/5] core
  ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
  ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
  ARM: OMAP: Update dmtimers
  ARM: OMAP: Make clock variables static
  ARM: OMAP: Fix GPMC compilation when DEBUG is defined
  ARM: OMAP: Mux updates for external DMA and GPIO
  ...

1 files changed, 23 insertions, 14 deletions

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 7edf0f69da1e..d1b648a4efbf 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -659,26 +659,35 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 
                 /* Isolate control register */
                 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-                div_off = clk->src_offset;
+                div_off = clk->rate_offset;
 
                 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
-                if(validrate != rate)
+                if (validrate != rate)
                         return(ret);
 
                 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
                 if (div_sel == 0)
                         return ret;
 
-                if(clk->flags & CM_SYSCLKOUT_SEL1){
-                        switch(new_div){
-                        case 16: field_val = 4; break;
-                        case 8:  field_val = 3; break;
-                        case 4:  field_val = 2; break;
-                        case 2:  field_val = 1; break;
-                        case 1:  field_val = 0; break;
+                if (clk->flags & CM_SYSCLKOUT_SEL1) {
+                        switch (new_div) {
+                        case 16:
+                                field_val = 4;
+                                break;
+                        case 8:
+                                field_val = 3;
+                                break;
+                        case 4:
+                                field_val = 2;
+                                break;
+                        case 2:
+                                field_val = 1;
+                                break;
+                        case 1:
+                                field_val = 0;
+                                break;
                         }
-                }
-                else
+                } else
                         field_val = new_div;
 
                 reg = (void __iomem *)div_sel;
@@ -743,7 +752,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
                         val = 0x2;
                 break;
         case CM_WKUP_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL2_CORE;
+                src_reg_addr = (u32)&CM_CLKSEL_WKUP;
                 mask = 0x3;
                 if (src_clk == &func_32k_ck)
                         val = 0x0;
@@ -783,9 +792,9 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
                         val = 0;
                 if (src_clk == &sys_ck)
                         val = 1;
-                if (src_clk == &func_54m_ck)
-                        val = 2;
                 if (src_clk == &func_96m_ck)
+                        val = 2;
+                if (src_clk == &func_54m_ck)
                         val = 3;
                 break;
         }