diff options
author | Paul Walmsley <paul@pwsan.com> | 2009-05-12 19:27:10 -0400 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-05-12 19:27:10 -0400 |
commit | b7aee4bfa7cad909220491214037731c1edb510a (patch) | |
tree | e8f01165e2e8b92e1eaef40badc6ad55f4dbb122 /arch/arm/mach-omap2/clock.c | |
parent | 4519c2bf433b97d091635eb51e4ba8ffa1c84d62 (diff) |
OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code
The CORE DPLL M2 frequency change code should use pr_debug(), not
pr_info(), for its debug messages. Same with
omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR ..
into pr_err().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 4247a1534411..8935a8b26186 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -547,8 +547,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
547 | const struct clksel_rate *clkr; | 547 | const struct clksel_rate *clkr; |
548 | u32 last_div = 0; | 548 | u32 last_div = 0; |
549 | 549 | ||
550 | printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", | 550 | pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", |
551 | clk->name, target_rate); | 551 | clk->name, target_rate); |
552 | 552 | ||
553 | *new_div = 1; | 553 | *new_div = 1; |
554 | 554 | ||
@@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
562 | 562 | ||
563 | /* Sanity check */ | 563 | /* Sanity check */ |
564 | if (clkr->div <= last_div) | 564 | if (clkr->div <= last_div) |
565 | printk(KERN_ERR "clock: clksel_rate table not sorted " | 565 | pr_err("clock: clksel_rate table not sorted " |
566 | "for clock %s", clk->name); | 566 | "for clock %s", clk->name); |
567 | 567 | ||
568 | last_div = clkr->div; | 568 | last_div = clkr->div; |
@@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
574 | } | 574 | } |
575 | 575 | ||
576 | if (!clkr->div) { | 576 | if (!clkr->div) { |
577 | printk(KERN_ERR "clock: Could not find divisor for target " | 577 | pr_err("clock: Could not find divisor for target " |
578 | "rate %ld for clock %s parent %s\n", target_rate, | 578 | "rate %ld for clock %s parent %s\n", target_rate, |
579 | clk->name, clk->parent->name); | 579 | clk->name, clk->parent->name); |
580 | return ~0; | 580 | return ~0; |
@@ -582,8 +582,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
582 | 582 | ||
583 | *new_div = clkr->div; | 583 | *new_div = clkr->div; |
584 | 584 | ||
585 | printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, | 585 | pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, |
586 | (clk->parent->rate / clkr->div)); | 586 | (clk->parent->rate / clkr->div)); |
587 | 587 | ||
588 | return (clk->parent->rate / clkr->div); | 588 | return (clk->parent->rate / clkr->div); |
589 | } | 589 | } |