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authorPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:14 -0500
committerPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:14 -0500
commitc4d7e58fb52c632d8e33cd23a4917d7a7f8302ac (patch)
tree20a56db9f93ff411fc439ea1961b1e51f2ecf15b /arch/arm/mach-omap2/clkt2xxx_apll.c
parentdac9a77120e2724e22696f06f3ecb4838da1e3e4 (diff)
OMAP2/3: PRM/CM: prefix OMAP2 PRM/CM functions with "omap2_"
Now that OMAP4-specific PRCM functions have been added, distinguish the existing OMAP2/3-specific PRCM functions by prefixing them with "omap2_". This patch should not result in any functional change. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Jarkko Nikula <jhnikula@gmail.com> Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_apll.c')
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 954d11f37542..f51cffd1fc53 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
49 49
50 apll_mask = EN_APLL_LOCKED << clk->enable_bit; 50 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
51 51
52 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); 52 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
53 53
54 if ((cval & apll_mask) == apll_mask) 54 if ((cval & apll_mask) == apll_mask)
55 return 0; /* apll already enabled */ 55 return 0; /* apll already enabled */
56 56
57 cval &= ~apll_mask; 57 cval &= ~apll_mask;
58 cval |= apll_mask; 58 cval |= apll_mask;
59 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); 59 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
60 60
61 omap2_cm_wait_idlest(cm_idlest_pll, status_mask, 61 omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
62 OMAP24XX_CM_IDLEST_VAL, clk->name); 62 OMAP24XX_CM_IDLEST_VAL, clk->name);
@@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk)
83{ 83{
84 u32 cval; 84 u32 cval;
85 85
86 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); 86 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
87 cval &= ~(EN_APLL_LOCKED << clk->enable_bit); 87 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
88 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); 88 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
89} 89}
90 90
91/* Public data */ 91/* Public data */
@@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void)
106{ 106{
107 u32 aplls, srate = 0; 107 u32 aplls, srate = 0;
108 108
109 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); 109 aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
110 aplls &= OMAP24XX_APLLS_CLKIN_MASK; 110 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
111 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; 111 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
112 112