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authorPaul Walmsley <paul@pwsan.com>2009-12-08 18:33:14 -0500
committerpaul <paul@twilight.(none)>2009-12-11 19:00:42 -0500
commit18862cbe47e37beba98f22c088fbe6fe029df889 (patch)
treebf5763c8bc4e8253cfbd71a36fd6aa25789d2667 /arch/arm/mach-omap2/Kconfig
parent1fda39e6fd13f9f74721d2127f27675a4a0878af (diff)
OMAP3: SDRC: Place SDRC AC timing and MR changes in CORE DVFS SRAM code behind Kconfig
The code that reprograms the SDRC memory controller during CORE DVFS, mach-omap2/sram34xx.S:omap3_sram_configure_core_dpll(), does not ensure that all L3 initiators are prevented from accessing the SDRAM before modifying the SDRC AC timing and MR registers. This can cause memory to be corrupted or cause the SDRC to enter an unpredictable state. This patch places that code behind a Kconfig option, CONFIG_OMAP3_SDRC_AC_TIMING for now, and adds a note explaining what is going on. Ideally the code can be added back in once supporting code is present to ensure that other initiators aren't touching the SDRAM. At the very least, these registers should be reprogrammable during kernel init to deal with buggy bootloaders. Users who know that all other system initiators will not be touching the SDRAM can also re-enable this Kconfig option. This is a modification of a patch originally written by Rajendra Nayak <rnayak@ti.com> (the original is at http://patchwork.kernel.org/patch/51927/). Rather than removing the code completely, this patch just comments it out. Thanks to Benoît Cousson <b-cousson@ti.com> and Christophe Sucur <c-sucur@ti.com> for explaining the technical basis for this and for explaining what can be done to make this path work in future code. Thanks to Richard Woodruff <r-woodruff2@ti.com>, Nishanth Menon <nm@ti.com>, and Olof Johansson <olof@lixom.net> for their comments. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Christophe Sucur <c-sucur@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-omap2/Kconfig')
-rw-r--r--arch/arm/mach-omap2/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7309aab305a9..0cd25ceadb43 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -128,3 +128,15 @@ config OMAP3_EMU
128 help 128 help
129 Say Y here to enable debugging hardware of omap3 129 Say Y here to enable debugging hardware of omap3
130 130
131config OMAP3_SDRC_AC_TIMING
132 bool "Enable SDRC AC timing register changes"
133 depends on ARCH_OMAP3 && ARCH_OMAP34XX
134 default n
135 help
136 If you know that none of your system initiators will attempt to
137 access SDRAM during CORE DVFS, select Y here. This should boost
138 SDRAM performance at lower CORE OPPs. There are relatively few
139 users who will wish to say yes at this point - almost everyone will
140 wish to say no. Selecting yes without understanding what is
141 going on could result in system crashes;
142